Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS), Volume 5 Issue 2, May 2006

Guest editorial: Concurrent hardware and software design for multiprocessor SoC
Ahmed Jerraya, Trevor Mudge
Pages: 259-262
DOI: 10.1145/1151074.1151075

A design methodology for application-specific networks-on-chip
Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat Chakradhar
Pages: 263-280
DOI: 10.1145/1151074.1151076
With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation...

UML-based multiprocessor SoC design framework
Tero Kangas, Petri Kukkala, Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Jouni Riihimäki, Kimmo Kuusilinna
Pages: 281-320
DOI: 10.1145/1151074.1151077
This paper describes a complete design flow for multiprocessor systems-on-chips (SoCs) covering the design phases from system-level modeling to FPGA prototyping. The design of complex heterogeneous systems is enabled by raising the abstraction level...

Energy-efficient embedded software implementation on multiprocessor system-on-chip with multiple voltages
Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
Pages: 321-341
DOI: 10.1145/1151074.1151078
This paper develops energy-driven completion ratio guaranteed scheduling techniques for the implementation of embedded software on multiprocessor systems with multiple supply voltages. We leverage application's performance requirements, uncertainties...

Scheduling refinement in abstract RTOS models
Fabiano Hessel, Vitor M. Da Rosa, Carlos Eduardo Reif, César Marcon, Tatiana Gadelha Serra Dos Santos
Pages: 342-354
DOI: 10.1145/1151074.1151079
Scheduling decision for real-time embedded software applications has a great impact on system performance and, therefore, is an important issue in RTOS design. Moreover, it is highly desirable to have the system designer able to evaluate and select...

Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms
Jingzhao Ou, Viktor K. Prasanna
Pages: 355-382
DOI: 10.1145/1151074.1151080
Configurable multiprocessor platforms consist of multiple soft processors configured on FPGA devices. They have become an attractive choice for implementing many computing applications. In addition to the various ways of distributing software...

Cache coherence tradeoffs in shared-memory MPSoCs
Mirko Loghi, Massimo Poncino, Luca Benini
Pages: 383-407
DOI: 10.1145/1151074.1151081
Shared memory is a common interprocessor communication paradigm for single-chip multiprocessor platforms. Snoop-based cache coherence is a very successful technique that provides a clean shared-memory programming abstraction in general-purpose chip...

A new efficient EDA tool design methodology
James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu
Pages: 408-430
DOI: 10.1145/1151074.1151082
New sophisticated EDA tools and methodologies will be needed to make products viable in the future marketplace by simplifying the various design stages. These tools will permit system design at a high abstraction level and enable automatic refinement...

A retargetable framework for instruction-set architecture simulation
Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra
Pages: 431-452
DOI: 10.1145/1151074.1151083
Instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high-performance simulation, the increasing variety of available...

Evaluating Network Processors using NetBench
Gokhan Memik, William H. Mangione-Smith
Pages: 453-471
DOI: 10.1145/1151074.1151084
The Network Processor market is one of the fastest growing segments of the microprocessor industry today. In spite of this increasing market importance, there does not exist a common framework to compare the performance of different Network Processor...

Dynamic allocation for scratch-pad memory using compile-time decisions
Sumesh Udayakumaran, Angel Dominguez, Rajeev Barua
Pages: 472-511
DOI: 10.1145/1151074.1151085
In this research, we propose a highly predictable, low overhead, and, yet, dynamic, memory-allocation strategy for embedded systems with scratch pad memory. A scratch pad is a fast compiler-managed SRAM memory that replaces the...