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Efficient software implementation of embedded communication protocol controllers using asynchronous software thread integration with time- and space-efficient procedure calls
Nagendra J. Kumar, Vasanth Asokan, Siddhartha Shivshankar, Alexander G. Dean
Article No.: 2
The overhead of context switching limits efficient scheduling of multiple concurrent threads on a uniprocessor when real-time requirements exist. A software-implemented protocol controller may be crippled by this problem. The available idle time may...
Power-efficient prefetching for embedded processors
Xiaotong Zhuang, Santosh Pande
Article No.: 3
Because of stringent power constraints, aggressive latency-hiding approaches, such as prefetching, are absent in the state-of-the-art embedded processors. There are two main reasons that make prefetching power inefficient. First, compiler-inserted...
The XTREM power and performance simulator for the Intel XScale core: Design and experiences
Gilberto Contreras, Margaret Martonosi, Jinzhang Peng, Guei-Yuan Lueh, Roy Ju
Article No.: 4
Managing power concerns in microprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these...
Link-time compaction and optimization of ARM executables
Bjorn De Sutter, Ludo Van Put, Dominique Chanet, Bruno De Bus, Koen De Bosschere
Article No.: 5
The overhead in terms of code size, power consumption, and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded world, where real-time constraints, battery life-time, and production...
Section: 1 - Special Section
The Molen compiler for reconfigurable processors
Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
Article No.: 6
In this paper, we describe the compiler developed to target the Molen reconfigurable processor and programming paradigm. The compiler automatically generates optimized binary code for C applications, based on pragma annotation of the code executed on...
Timing analysis for preemptive multitasking real-time systems with caches
Yudong Tan, Vincent Mooney
Article No.: 7
In this paper, we propose an approach to estimate the worst-case response time (WCRT) of each task in a preemptive multitasking single-processor real-time system utilizing an L1 cache. The approach combines intertask cache-eviction analysis and...
Safety verification of hybrid systems by constraint propagation-based abstraction refinement
Stefan Ratschan, Zhikun She
Article No.: 8
This paper deals with the problem of safety verification of nonlinear hybrid systems. We start from a classical method that uses interval arithmetic to check whether trajectories can move over the boundaries in a rectangular grid. We put this method...