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ACM Transactions on Embedded Computing Systems (TECS), Volume 8 Issue 2, January 2009

Energy-efficient encoding techniques for off-chip data buses
Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid Najjar
Article No.: 9
DOI: 10.1145/1457255.1457256

Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as they consume a significant amount of total power. Since the bus...

On the exploitation of loop-level parallelism in embedded applications
Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito
Article No.: 10
DOI: 10.1145/1457255.1457257

Advances in the silicon technology have enabled increasing support for hardware parallelism in embedded processors. Vector units, multiple processors/cores, multithreading, special-purpose accelerators such as DSPs or cryptographic engines, or a...

Throughput-driven synthesis of embedded software for pipelined execution on multicore architectures
Matin Hashemi, Soheil Ghiasi
Article No.: 11
DOI: 10.1145/1457255.1457258

We present a methodology for pipelined software synthesis of streaming applications. First, we develop a versatile task assignment algorithm capable of optimizing realistically-arbitrary cost functions for two cores. The algorithm is exact (i.e.,...

A comparison of software platforms for wireless sensor networks: MANTIS, TinyOS, and ZigBee
Mohammad Mostafizur Rahman Mozumdar, Luciano Lavagno, Laura Vanzago
Article No.: 12
DOI: 10.1145/1457255.1457264

Wireless sensor networks are characterized by very tight code size and power constraints and by a lack of well-established standard software development platforms such as Posix. In this article, we present a comparative study between a few fairly...

Modeling and analysis of core-centric network processors
Yi-Neng Lin, Ying-Dar Lin, Kuo-Kun Tseng, Yuan-Cheng Lai
Article No.: 13
DOI: 10.1145/1457255.1457260

Network processors can be categorized into two types, the coprocessors-centric model in which the data-plane is handled by coprocessors, and the core-centric model in which the core processes most of the data-plane packets yet offloading some...

Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems
Xiangrong Zhou, Peter Petrov
Article No.: 14
DOI: 10.1145/1457255.1457261

Preemptive multitasking is widely used in many low-cost and real-time embedded applications for its superior hardware utilization. The frequent and asynchronous context switches, however, require the preservation and restoration of the task state,...

Low-latency time-portable real-time programming with Exotasks
Joshua Auerbach, David F. Bacon, Daniel Iercan, Christoph M. Kirsch, V. T. Rajan, Harald Röck, Rainer Trummer
Article No.: 15
DOI: 10.1145/1457255.1457262

Exotasks are a novel Java programming construct that achieve three important goals. They achieve low latency while allowing the fullest use of Java language features, compared to previous attempts to restrict the Java language for use in...

Register coalescing techniques for heterogeneous register architecture with copy sifting
Minwook Ahn, Yunheung Paek
Article No.: 16
DOI: 10.1145/1457255.1457263

Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous...