enter search term and/or author name
Guest editorial CAPA'08 configurable computing: Configuring algorithms, processes, and architecture issue I: Configuring algorithms and processes
Dr. Toomas P. Plaks, Neil Bergmann, Bernard Pottier
Article No.: 1
Reconfiguration of IIR filters in response to computer resource availability
B. H. Ferri, A. A. Ferri
Article No.: 2
This article explores methods to reconfigure infinite impulse response (IIR) filters in processes that utilize computer resource management. A high-performance mode uses a full-length IIR filter, while low resources or a desire to conserve power...
A truly two-dimensional systolic array FPGA implementation of QR decomposition
Xiaojun Wang, Miriam Leeser
Article No.: 3
We have implemented a two-dimensional systolic array QR decomposition on a Xilinx Virtex5 FPGA using the Givens rotation algorithm. QR decomposition is a key step in many DSP applications including sonar beamforming, channel equalization, and 3G...
Application development with the FlexWAFE real-time stream processing architecture for FPGAs
Amilcar Do Carmo Lucas, Henning Sahlbach, Sean Whitty, Sven Heithecker, Rolf Ernst
Article No.: 4
The challenges posed by complex real-time digital image processing at high resolutions cannot be met by current state-of-the-art general-purpose or DSP processors, due to the lack of processing power. On the other hand, large arrays of FPGA-based...
An approximation algorithm for scheduling on heterogeneous reconfigurable resources
Ani Nahapetian, Philip Brisk, Soheil Ghiasi, Majid Sarrafzadeh
Article No.: 5
Dynamic reconfiguration imposes significant penalties in terms of performance and energy. Scheduling the execution of tasks on a dynamically reconfigurable device is therefore of critical importance. Likewise, other application domains have cost...
The difficult aspect of hardware reconfiguration is not creating the computational blocks, which are generally available from FPGA vendors and third parties, but linking the blocks in a manner that suits each application's unique connectivity,...
A packet-switched network architecture for reconfigurable computing
Scott Lloyd, Quinn Snell
Article No.: 7
A packet-switched network architecture named Qnet and programming interface is presented that simplifies the integration of reconfigurable computing modules within a Field-Programmable Gate Array (FPGA). Qnet provides an abstraction layer to the...
ReconOS: Multithreaded programming for reconfigurable computers
Enno Lübbers, Marco Platzner
Article No.: 8
Rising logic densities together with the inclusion of dedicated processor cores push reconfigurable devices from being applied for glue logic and prototyping towards implementing complete reconfigurable systems-on-chip. The mix of fast CPU cores...
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
Jian Huang, Matthew Parris, Jooheung Lee, Ronald F. Demara
Article No.: 9
In this article, we propose field programmable gate array-based scalable architecture for discrete cosine transform (DCT) computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial...