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Guest editorial CAPA'08 Configurable computing: Configuring algorithms, processes, and architecture Issue II: Configuring hardware architecture
Dr. Toomas P. Plaks, Neil Bergmann, Bernard Pottier
Article No.: 10
REDEFINE: Runtime reconfigurable polymorphic ASIC
Mythri Alle, Keshavan Varadarajan, Alexander Fell, Ramesh Reddy C., Nimmy Joseph, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsh Rao, S. K. Nandy, Ranjani Narayan
Article No.: 11
Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically...
FPGA placement using space-filling curves: Theory meets practice
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy, Subhasis Bhattacharjee
Article No.: 12
Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce a near-optimal solution but without theoretical guarantee on its quality....
Power scalability in a mesh-connected reconfigurable architecture
Article No.: 13
We analyze power--area--performance trade-offs within a hypothetical mesh-connected reconfigurable architecture. A new analytic model relating area, power, and performance based on a simple VLSI complexity metric, is used to determine the behavior...
Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit
Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer
Article No.: 14
As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration...