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ACM Transactions on Embedded Computing Systems (TECS), Volume 11S Issue 1, June 2012

Introduction to the Special Section on ESTIMedia’08
Mladen Berekovic, Samarjit Chakraborty, Petru Eles, Andy D. Pimentel
Article No.: 11
DOI: 10.1145/2180887.2180891

Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications
Jun Zhu, Ingo Sander, Axel Jantsch
Article No.: 12
DOI: 10.1145/2180887.2180888

We propose a performance analysis framework for adaptive real-time synchronous data flow streaming applications on runtime reconfigurable FPGAs. As the main contribution, we present a constraint based approach to capture both streaming application...

Parallelization of Belief Propagation on Cell Processors for Stereo Vision
Kun-Yuan Hsieh, Chi-Hua Lai, Shang-Hong Lai, Jenq Kuen Lee
Article No.: 13
DOI: 10.1145/2180887.2180889

Markov random field models provide a robust formulation for the stereo vision problem of inferring three-dimensional scene geometry from two images taken from different viewpoints. One of the most advanced algorithms for solving the associated...

Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures
Andrei Terechko, Jan Hoogerbrugge, Ghiath Alkadi, Surendra Guntur, Anirban Lahiri, Marc Duranton, Clemens Wüst, Phillip Christie, Axel Nackaerts, Aatish Kumar
Article No.: 14
DOI: 10.1145/2180887.2180890

Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design...

Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications
Amin Khajeh, Minyoung Kim, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi
Article No.: 15
DOI: 10.1145/2180887.2180892

In this article, we propose a cross-layer algorithm/architecture coexploration for wireless multimedia systems to coordinate interactions among sublayer optimizers for improvements in energy/QoS/reliability. By exploiting the inherent redundancy...

Storage Optimization through Offset Assignment with Variable Coalescing
Hassan Salamy, J. Ramanujam
Article No.: 16
DOI: 10.1145/2180887.2180893

Most modern digital signal processors (DSPs) provide multiple address registers and a dedicated address generation unit (AGU) which performs address generation in parallel to instruction execution. There is no address computation overhead if the...

Introduction to the Special Section on SCOPES’09
Heiko Falk, Peter Marwedel
Article No.: 17
DOI: 10.1145/2180887.2180894

FlashLight: A Lightweight Flash File System for Embedded Systems
Jaegeuk Kim, Hyotaek Shim, Seon-Yeong Park, Seungryoul Maeng, Jin-Soo Kim
Article No.: 18
DOI: 10.1145/2180887.2180895

A very promising approach for using NAND flash memory as a storage medium is a flash file system. In order to design a higher-performance flash file system, two issues should be considered carefully. One issue is the design of an efficient index...

Integrated Code Generation for Loops
Mattias Eriksson, Christoph Kessler
Article No.: 19
DOI: 10.1145/2180887.2180896

Code generation in a compiler is commonly divided into several phases: instruction selection, scheduling, register allocation, spill code generation, and, in the case of clustered architectures, cluster assignment. These phases are interdependent;...

Adaptive Source-Level Data Assignment to Dual Memory Banks
Alastair Murray, Björn Franke
Article No.: 20
DOI: 10.1145/2180887.2180897

Dual memory banks provide extra memory bandwidth to DSP applications and enable simultaneous access to two operands if the data is partitioned appropriately. Fully automated and compiler integrated approaches to data partitioning and memory bank...

SSI Properties Revisited
Benoit Boissinot, Philip Brisk, Alain Darte, Fabrice Rastello
Article No.: 21
DOI: 10.1145/2180887.2180898

The static single information (SSI) form is an extension of the static single assignment (SSA) form, a well-established compiler intermediate representation that has been successfully used for numerous compiler analysis and optimizations. Several...

Statistical Performance Modeling in Functional Instruction Set Simulators
Björn Franke
Article No.: 22
DOI: 10.1145/2180887.2180899

Despite the recent progress in improving the speed of instruction-accurate simulators cycle-accurate simulation is still prohibitively slow for all but the most basic programs. In this article we present a statistical machine...

Computer-Aided Recoding to Create Structured and Analyzable System Models
Pramod Chandraiah, Rainer Dömer
Article No.: 23
DOI: 10.1145/2180887.2180900

In embedded system design, the quality of the input model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-written system model, tools today are effective in generating working implementations....

Exploring and Predicting the Effects of Microarchitectural Parameters and Compiler Optimizations on Performance and Energy
Christophe Dubach, Timothy M. Jones, Michael F. P. O’Boyle
Article No.: 24
DOI: 10.1145/2180887.2180901

Embedded processor performance is dependent on both the underlying architecture and the compiler optimizations applied. However, designing both simultaneously is extremely difficult to achieve due to the time constraints designers must work under....