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Introduction to the special section on ESTIMedia'12
Jian-Jia Chen, Maurizio Palesi
Article No.: 32
A novel low-power embedded object recognition system working at multi-frames per second
Antonis Nikitakis, Savvas Papaioannou, Ioannis Papaefstathiou
Article No.: 33
One very important challenge in the field of multimedia is the implementation of fast and detailed Object Detection and Recognition systems. In particular, in the current state-of-the-art mobile multimedia systems, it is highly desirable to detect...
Mapping of streaming applications considering alternative application specifications
Jiali Teddy Zhai, Hristo Nikolov, Todor Stefanov
Article No.: 34
Streaming applications often require a parallel Model of Computation (MoC) to specify their application behavior and to facilitate mapping onto Multi-Processor System-on-Chip (MPSoC) platforms. Various performance requirements and resource budgets...
Sequential specification of time-aware stream processing applications
Stefan J. Geuns, Joost P. H. M. Hausmans, Marco J. G. Bekooij
Article No.: 35
Automatic parallelization of Nested Loop Programs (NLPs) is an attractive method to create embedded real-time stream processing applications for multi-core systems. However, the description and parallelization of applications with a time dependent...
A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memory
Daeyoung Lee, Hyunok Oh
Article No.: 36
This article proposes a lifetime aware buffer assignment method for streaming applications like multimedia specified in a synchronous dataflow (SDF) graph on a DRAM/PRAM hybrid memory in which the endurance of PRAM is limited. We determine whether...
Enhancing user experiences by exploiting energy and launch delay trade-off of mobile multimedia applications
Yi-Fan Chung, Yin-Tsung Lo, Chung-Ta King
Article No.: 37
Launch delay has been an important factor affecting users' experiences in mobile multimedia applications. To launch applications quickly, modern mobile systems such as Android usually keep inactive applications in the background and manage them...
Synchronous programming of device drivers for global resource control in embedded operating systems
Nicolas Berthier, Florence Maraninchi, Laurent Mounier
Article No.: 39
In embedded systems, controlling a shared resource like a bus, or improving a property like power consumption, may be hard to achieve when programming device drivers individually. In this article, we propose a global resource control...
To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis.
Introduction to the special section on rigorous embedded systems design
Joseph Sifakis, Lothar Thiele, Reinhard Wilhelm
Article No.: 41
The sensitivity of a cache replacement policy expresses to what extent the execution history may influence the number of cache hits and misses during program execution. We present an algorithm to compute the sensitivity of a replacement policy. We...
Memory reservation in embedded systems is a prevalent approach to provide a physically contiguous memory region to its integrated devices, such as a camera device and a video decoder. Inefficiency of the memory reservation becomes a more...
Heuristic search for adaptive, defect-tolerant multiprocessor arrays
Vasileios Vasilikos, Georgios Smaragdos, Christos Strydis, Ioannis Sourdis
Article No.: 44
In this article, new heuristic-search methods and algorithms are presented for enabling highly efficient and adaptive, defect-tolerant multiprocessor arrays. We consider systems where a homogeneous multiprocessor array lies on top of...
This article presents FUSE, an approach for modeling and implementing embedded software components which starts from a main-stream programming language and brings some of the key concepts of Statecharts as first-class elements within this...
Introduction to the special section on multiprocessor system-on-chip for cyber-physical systems
Article No.: 46
Parallel programming patterns for multi-processor SoC: Application to video processing
Pierre G. Paulin, Ali Erdem Özcan, Vincent Gagné, Bruno Lavigueur, Olivier Benny
Article No.: 47
Efficient, scalable and productive parallel programming is a major challenge for exploiting the future multi-processor SoC platforms. This article presents the MultiFlex programming environment which has been developed to address this...
Predictability for timing and temperature in multiprocessor system-on-chip platforms
Lothar Thiele, Lars Schor, Iuliana Bacivarov, Hoeseok Yang
Article No.: 48
High computational performance in multiprocessor system-on-chips (MPSoCs) is constrained by the ever-increasing power densities in integrated circuits, so that nowadays MPSoCs face various thermal issues. For instance, high chip temperatures may...
Abhijit Davare, Douglas Densmore, Liangpeng Guo, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli, Alena Simalatsar, Qi Zhu
Article No.: 49
Cyber-Physical Systems are integrations of computation and physical processes and as such, will be increasingly relevant to industry and people. The complexity of designing CPS resides in their heterogeneity. Heterogeneity manifest itself...
Pacemaker control of heart rate variability: A cyber physical system perspective
Paul Bogdan, Siddharth Jain, Radu Marculescu
Article No.: 50
Cardiac diseases, like those related to abnormal heart rate activity, have an enormous economic and psychological impact worldwide. The approaches used to control the behavior of modern pacemakers ignore the fractal nature of heart rate activity....
Reliable and adaptive network-on-chip architectures for cyber physical systems
Diana Göhringer, Lukas Meder, Oliver Oey, Jürgen Becker
Article No.: 51
Reliability in embedded systems is crucial for many application domains. Especially, for safety critical application, as they can be found in the automotive and avionic domain, a high reliability has to be ensured. The technology in chip...
Power minimization for dynamically reconfigurable FPGA partitioning
Tzu-Chiang Tai, Yen-Tai Lai
Article No.: 52
Dynamically reconfigurable FPGA (DRFPGA) implements a given circuit system by partitioning it into stages and then executing each stage sequentially. Traditionally, the number of communication buffers is minimized. In this article, we study the...
Dynamic task partition for video decoding on heterogeneous dual-core platforms
Chun-Jen Tsai, Tsung-Fan Shen, Pei-Ching Liao
Article No.: 53
This article presents the design of a video decoder using dynamic task partition approach on a heterogeneous dual-core embedded platform. For such systems, static task partition between the two cores at design time is a typical approach for...
A distributed timing synchronization technique for parallel multi-core instruction-set simulation
Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay
Article No.: 54
As multi-core architecture has become the mainstream, the corresponding multi-core instruction-set simulation (MCISS) is also needed to aid system development. Ideally, we may run a MCISS in parallel to enhance the simulation speed. However, the...
Adaptive loop caching using lightweight runtime control flow analysis
Marisha Rawlins, Ann Gordon-Ross
Article No.: 55
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code (critical regions) in a more energy efficient structure than the level one cache. However, due to code structure...
As the number of cores integrated on a single chip continues to increase, communication has the potential to become a severe bottleneck to overall system performance. The presence of thread sharing and the distribution of data across cache banks...
We introduce Hermes, a lightweight smart shoe and its supporting infrastructure aimed at extending gait and instability analysis and human instability/balance monitoring outside of a laboratory environment. We aimed to create a scientific...
GALS-HMP: A heterogeneous multiprocessor for embedded applications
Zoran Salcic, Avinash Malik
Article No.: 58
We present a new heterogeneous multiprocessor (GALS-HMP) for the execution of Globally Asynchronous Locally Synchronous (GALS) programming languages. It specifically targets SystemJ GALS language, which extends Java with asynchronous and...
MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining
Luis Angel D. Bathen, Yongjin Ahn, Sudeep Pasricha, Nikil D. Dutt
Article No.: 59
The increasing demand for low-power and high-performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency requirements under a tight power budget. As technology scales, it is...
Implementation strategy for downgraded flash-memory storage devices
Jen-Wei Hsieh, Yuan-Hao Chang, Yuan-Sheng Chu
Article No.: 60
In recent years, low-cost flash-memory devices have contributed greatly to the rapid growth of the flash memory market. Given that the most of the cost of such devices is the cost of the flash-memory chips, many vendors are managing the cost of...
SystemC is widely used for modeling and simulation in hardware/software co-design. However, existing verification techniques are mostly ad-hoc and non-systematic. In this article, we present a systematic, comprehensive, and formally founded...
Hot-LSNs distributing wear-leveling algorithm for flash memory
Se Jin Kwon, Tae-Sun Chung
Article No.: 62
Flash memory offers attractive features, such as non-volatile, shock resistance, fast access and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, the flash...
A new architecture, QUKU, is proposed for implementing stream-based algorithms on FPGAs, which combines the advantages of FPGA and Coarse Grain Reconfigurable Arrays (CGRAs). QUKU consists of a dynamically reconfigurable, coarse-grain Processing...
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla
Article No.: 64
Multicore processors are an effective solution to cope with the performance requirements of real-time embedded systems due to their good performance-per-watt ratio and high performance capabilities. Unfortunately, their use in integrated...
Fiat-shamir identification scheme immune to the hardware fault attacks
Sung-Kyoung Kim, Tae Hyun Kim, Seokhie Hong
Article No.: 65
The Fiat-Shamir identification scheme is popular for “light” consumer devices, such as smart cards, in a wide range of consumer services. However, it can be vulnerable to fault attacks, even though a cryptographic algorithm is...
Embedded systems security is a significant requirement in emerging environments, considering the increasing deployment of embedded systems in several application domains. The large number of deployed embedded systems, their limited resources and...