Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS), Volume 12 Issue 3, March 2013

Schedulability analysis of EDF-scheduled embedded real-time systems with resource sharing
Fengxiang Zhang, Alan Burns
Article No.: 67
DOI: 10.1145/2442116.2442117

Earliest Deadline First (EDF) is the most widely studied optimal dynamic scheduling algorithm for uniprocessor real-time systems. In the existing literature, however, there is no complete exact analysis for EDF scheduling when both resource...

Using memory profile analysis for automatic synthesis of pointers code
Yosi Ben-Asher, Nadav Rotem
Article No.: 68
DOI: 10.1145/2442116.2442118

One of the main advantages of high-level synthesis (HLS) is the ability to synthesize circuits that can access multiple memory banks in parallel. Current HLS systems synthesize parallel memory references based on explicit array declarations in the...

Robustness analysis for battery-supported cyber-physical systems
Fumin Zhang, Zhenwu Shi, Shayok Mukhopadhyay
Article No.: 69
DOI: 10.1145/2442116.2442119

This article establishes a novel analytical approach to quantify robustness of scheduling and battery management for battery supported cyber-physical systems. A dynamic schedulability test is introduced to determine whether tasks are schedulable...

MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems
Nikolaos S. Voros, Michael Hübner, Jürgen Becker, Matthias Kühnle, Florian Thomaitiv, Arnaud Grasset, Paul Brelet, Philippe Bonnot, Fabio Campi, Eberhard Schüler, Henning Sahlbach, Sean Whitty, Rolf Ernst, Enrico Billich, Claudia Tischendorf, Ulrich Heinkel, Frank Ieromnimon, Dimitrios Kritharidis, Axel Schneider, Joachim Knaeblein, Wolfram Putzke-Röming
Article No.: 70
DOI: 10.1145/2442116.2442120

Recently, system designers are facing the challenge of developing systems that have diverse features, are more complex and more powerful, with less power consumption and reduced time to market. These contradictory constraints have forced...

Configurable memory security in embedded systems
Jérémie Crenne, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan
Article No.: 71
DOI: 10.1145/2442116.2442121

System security is an increasingly important design criterion for many embedded systems. These systems are often portable and more easily attacked than traditional desktop and server computing systems. Key requirements for system security include...

Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems
Shaoshan Liu, Richard Neil Pittman, Alessandro Forin, Jean-Luc Gaudiot
Article No.: 72
DOI: 10.1145/2442116.2442122

One major advantage of reconfigurable computing systems is their ability to reconfigure hardware at runtime. In this paper, we study the feasibility of achieving energy efficiency in reconfigurable computing systems (e.g., FPGAs) through runtime...

Providing DoS resistance for signature-based broadcast authentication in sensor networks
Qi Dong, Donggang Liu, Peng Ning
Article No.: 73
DOI: 10.1145/2442116.2442123

Recent studies have demonstrated that it is feasible to perform public key cryptographic operations on resource-constrained sensor platforms. However, the significant energy consumption introduced by public key operations makes any public...

A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs
Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich
Article No.: 74
DOI: 10.1145/2442116.2442124

In this article, an efficient rule-based clustering algorithm for static dataflow subgraphs in a dynamic dataflow graph is presented. The clustered static dataflow actors are quasi-statically scheduled, in such a way that the global...

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
Luciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Moller, Leandro Soares Indrusiak, Gilles Sassatelli, Pascal Benoit, Manfred Glesner, Michel Robert, Fernando Moraes
Article No.: 75
DOI: 10.1145/2442116.2442125

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the...

Joint variable partitioning and bank selection instruction optimization for partitioned memory architectures
Tiantian Liu, Chun Jason Xue, Minming Li
Article No.: 76
DOI: 10.1145/2442116.2442126

About 55% of all CPUs sold in the world are 8-bit microcontrollers or microprocessors which can only access limited memory space without extending address buses. Partitioned memory with bank switching is a technique to increase memory size...

Write activity reduction on non-volatile main memories for embedded chip multiprocessors
Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, Edwin H.-M. Sha
Article No.: 77
DOI: 10.1145/2442116.2442127

Recent advances in circuit and semiconductor technologies have pushed Non-Volatile Memory (NVM) technologies into a new era. These technologies exhibit appealing properties such as low power consumption, non-volatility, shock-resistivity, and high...

Partitioning sporadic task systems upon memory-constrained multiprocessors
Sanjoy Baruah
Article No.: 78
DOI: 10.1145/2442116.2442128

Most prior theoretical research on real-time partitioning algorithms for multiprocessor platforms has focused on ensuring that the cumulative computing requirements of the tasks assigned to each processor does not exceed the processor's processing...

A hard real-time capable multi-core SMT processor
Marco Paolieri, Jörg Mische, Stefan Metzlaff, Mike Gerdes, Eduardo Quiñones, Sascha Uhrig, Theo Ungerer, Francisco J. Cazorla
Article No.: 79
DOI: 10.1145/2442116.2442129

Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case...

Detection of harmful schizophrenic statements in esterel
Jeong-Han Yun, Chul-Joo Kim, Seonggun Kim, Kwang-Moo Choe, Taisook Han
Article No.: 80
DOI: 10.1145/2442116.2442130

In imperative synchronous languages, a statement is called schizophrenic if it is executed more than once in a single clock. When a schizophrenic statement is translated into a circuit, the circuit can behave abnormally because of the multiple...

Energy-efficient and high-performance software architecture for storage class memory
Seungjae Baek, Jongmoo Choi, Donghee Lee, Sam H. Noh
Article No.: 81
DOI: 10.1145/2442116.2442131

Recently, interest in incorporating Storage Class Memory (SCM), which blurs the distinction between memory and storage, into mainstream computing has been increasing rapidly. In this paper, we address the emerging questions regarding the use of...

High-performance and low-energy buffer mapping method for multiprocessor DSP systems
Dongwon Lee, Marilyn Wolf, Shuvra S. Bhattacharyya
Article No.: 82
DOI: 10.1145/2442116.2442132

When implementing digital signal processing (DSP) applications onto multiprocessor systems, one significant problem in the viewpoints of performance is the memory wall. In this paper, to help alleviate the memory wall problem, we propose a novel,...

Compositionality in synchronous data flow: Modular code generation from hierarchical SDF graphs
Stavros Tripakis, Dai Bui, Marc Geilen, Bert Rodiers, Edward A. Lee
Article No.: 83
DOI: 10.1145/2442116.2442133

Hierarchical SDF models are not compositional: a composite SDF actor cannot be represented as an atomic SDF actor without loss of information that can lead to rate inconsistency or deadlock. Motivated by the need for incremental and modular code...

Market-based resource allocation for distributed data processing in wireless sensor networks
Andrew T. Zimmerman, Jerome P. Lynch, Frank T. Ferrese
Article No.: 84
DOI: 10.1145/2442116.2442134

In recent years, improved wireless technologies have enabled the low-cost deployment of large numbers of sensors for a wide range of monitoring applications. Because of the computational resources (processing capability, storage capacity, etc.)...

Profiling and online system-level performance and power estimation for dynamically adaptable embedded systems
Jingqing Mu, Karthik Shankar, Roman Lysecky
Article No.: 85
DOI: 10.1145/2442116.2442135

Significant research has demonstrated the performance and power benefits of runtime dynamic reconfiguration of FPGAs and microprocessor/FPGA devices. For dynamically reconfigurable systems, in which the selection of hardware coprocessors to...