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Introduction to the special section on ESTIMedia'10
Naehyuck Chang, Jian-Jia Chen
Article No.: 26
A system-level infrastructure for multidimensional MP-SoC design space co-exploration
Zai Jian Jia, Tomás Bautista, Antonio Núñez, Andy D. Pimentel, Mark Thompson
Article No.: 27
In this article, we present a flexible and extensible system-level MP-SoC design space exploration (DSE) infrastructure, called NASA. This highly modular framework uses well-defined interfaces to easily integrate different system-level simulation...
Automated generation of polyhedral process networks from affine nested-loop programs with dynamic loop bounds
Dmitry Nadezhkin, Hristo Nikolov, Todor Stefanov
Article No.: 28
The Process Networks (PNs) is a suitable parallel model of computation (MoC) used to specify embedded streaming applications in a parallel form facilitating the efficient mapping onto embedded parallel execution platforms. Unfortunately,...
An analytical model for on-chip interconnects in multimedia embedded systems
Yulei Wu, Geyong Min, Dakai Zhu, Laurence T. Yang
Article No.: 29
The traffic pattern has significant impact on the performance of network-on-chip. Many recent studies have shown that multimedia applications can be supported in on-chip interconnects. Driven by the motivation of evaluating on-chip interconnects...
Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors
Weijia Che, Karam S. Chatha
Article No.: 30
In this article, we propose a heuristic algorithm for scheduling synchronous data flow (SDF) models on scratch pad memory (SPM) enhanced processors with the objective of minimizing its steady-state execution time. The task involves partitioning...
Improving the fault resilience of an H.264 decoder using static analysis methods
Florian Schmoll, Andreas Heinig, Peter Marwedel, Michael Engel
Article No.: 31
Fault tolerance rapidly evolves into one of the most significant design objectives for embedded systems due to reduced semiconductor structures and supply voltages. However, resource-constrained systems cannot afford traditional error correction...
Predictable and configurable component-based scheduling in the C
Gabriel Parmer, Richard West
Article No.: 32
This article presents the design of user-level scheduling hierarchies in the C
Accelerating radiation dose calculation: A multi-FPGA solution
Bo Zhou, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X. Yu
Article No.: 33
Remarkable progress has been made in the past few decades in various aspects of radiation therapy (RT). However, some of these promising technologies, such as image-guided online replanning and arc therapy, rely heavily on the availability of fast...
Configuration and operation of networked control systems over heterogeneous WSANs
Pedro Furtado, José Cecílio
Article No.: 34
There have been both research and commercial advances on applying Wireless Sensor and Actuator Networks (WSN) in industrial premises. These have cost advantages related to avoiding some cabled deployments. A possible architecture involves a...
System-level memory management based on statistical variability compensation for frame-based applications
Concepción Sanz, José Ignacio Gómez, Christian Tenllado, Manuel Prieto, Francky Catthoor
Article No.: 35
Process variability and dynamic domains increase the uncertainty of embedded systems and force designers to apply pessimistic designs, which become unnecessarily conservative and have a tremendous impact on both performance and energy consumption....
Adaptive scheduling of real-time systems cosupplied by renewable and nonrenewable energy sources
Morteza Mohaqeqi, Mehdi Kargahi, Maryam Dehghan
Article No.: 36
Energy management is an important issue in today's real-time systems due to the high costs of energy supplying. Using renewable, like wave, wind, and solar energy sources seem promising methods to address this issue. However, because of the...
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
Chen-Kang Lo, Mao-Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh
Article No.: 37
Although pipelined/out-of-order (PL/OO) execution features are commonly supported by the state-of-the-art bus designs, no existing manual Transaction-Level-Modeling (TLM) approaches can effectively construct fast and accurate simulation models for...
Software-based register file vulnerability reduction for embedded processors
Jongeun Lee, Aviral Shrivastava
Article No.: 38
Register File (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor, but also since it is one of the...
Models for characterizing noise based PCMOS circuits
Anshul Singh, Arindam Basu, Keck-Voon Ling, Vincent J. Mooney III
Article No.: 39
Quick and accurate error-rate prediction of Probabilistic CMOS (PCMOS) circuits is crucial for their systematic design and performance evaluation. While still in the early stage of research, PCMOS has shown potential to drastically reduce energy...
Power-aware dynamic memory management on many-core platforms utilizing DVFS
Iraklis Anagnostopoulos, Jean-Michel Chabloz, Ioannis Koutras, Alexandros Bartzas, Ahmed Hemani, Dimitrios Soudris
Article No.: 40
Today multicore platforms are already prevalent solutions for modern embedded systems. In the future, embedded platforms will have an even more increased processor core count, composing many-core platforms. In addition, applications are becoming...