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Application-aware adaptive cache architecture for power-sensitive mobile processors
Garo Bournoutian, Alex Orailoglu
Article No.: 41
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for general-purpose processors. All the while, it is also expected that these mobile...
GPU-optimized volume ray tracing for massive numbers of rays in radiotherapy
Bo Zhou, Kai Xiao, Danny Z. Chen, X. Sharon Hu
Article No.: 42
Ray tracing within a uniform grid volume is a fundamental process invoked frequently by many applications, especially radiation-dose calculation methods in radiotherapy. However, the conflicting features between the GPU memory architecture and the...
An analytical approach for fast and accurate design space exploration of instruction caches
Yun Liang, Tulika Mitra
Article No.: 43
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip area. Simulation, in particular trace-driven simulation, is widely used to estimate cache hit...
Analyzing an embedded sensor with timed automata in uppaal
Timothy Bourke, Arcot Sowmya
Article No.: 44
An infrared sensor is modeled and analyzed in Uppaal. The sensor typifies the sort of component that engineers regularly integrate into larger systems by writing interface hardware and software.
In all, three main models are developed. In...
The stream-processing model is a natural fit for multicore systems because it exposes the inherent locality and concurrency of a program and highlights its separable tasks for efficient parallel implementations. We present flexible filters,...
Throughput-memory footprint trade-off in synthesis of streaming software on embedded multiprocessors
Matin Hashemi, Mohammad H. Foroozannejad, Soheil Ghiasi
Article No.: 46
We study the trade-off between throughput and memory footprint of embedded software that is synthesized from acyclic static dataflow (task graph) specifications targeting distributed memory multiprocessors. We identify iteration overlapping as a...
A regression test selection technique for embedded software
Swarnendu Biswas, Rajib Mall, Manoranjan Satpathy
Article No.: 47
The current approaches for regression test selection of embedded programs are usually based on data- and control-dependency analyses, often augmented with human reasoning. Existing techniques do not take into account additional execution...
A theory of robust omega-regular software synthesis
Rupak Majumdar, Elaine Render, Paulo Tabuada
Article No.: 48
A key property for systems subject to uncertainty in their operating environment is robustness: ensuring that unmodeled but bounded disturbances have only a proportionally bounded effect upon the behaviors of the system. Inspired by ideas...
Energy-aware code motion for GPU shader processors
Yi-Ping You, Shen-Hong Wang
Article No.: 49
Graphics processing units (GPUs) are now being widely adopted in system-on-a-chip designs, and they are often used in embedded systems for manipulating computer graphics or even for general-purpose computation. Energy management is of concern to...
Register allocation for embedded systems to simultaneously reduce energy and temperature on registers
Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li
Article No.: 50
Energy and thermal issues are two important concerns for embedded system design. Diminished energy dissipation leads to a longer battery life, while reduced temperature hotspots decelerate the physical failure mechanisms. The instruction fetch...
Dynamic profiling and fuzzy-logic-based optimization of sensor network platforms
Adrian Lizarraga, Roman Lysecky, Susan Lysecky, Ann Gordon-Ross
Article No.: 51
The commercialization of sensor-based platforms is facilitating the realization of numerous sensor network applications with diverse application requirements. However, sensor network platforms are becoming increasingly complex to design and...
The benefits of using variable-length pipelined operations in high-level synthesis
Yosi Ben-Asher, Nadav Rotem
Article No.: 52
Current high-level synthesis systems synthesize arithmetic units of a fixed known number of stages, and the scheduler mainly determines when units are activated. We focus on scheduling techniques for the high-level synthesis of pipelined...
A resource-driven DVFS scheme for smart handheld devices
Yu-Ming Chang, Pi-Cheng Hsiu, Yuan-Hao Chang, Che-Wei Chang
Article No.: 53
Reducing the energy consumption of the emerging genre of smart handheld devices while simultaneously maintaining mobile applications and services is a major challenge. This work is inspired by an observation on the resource usage patterns of...
A hardware architecture for real-time object detection using depth and edge information
Christos Kyrkou, Christos Ttofis, Theocharis Theocharides
Article No.: 54
Emerging embedded 3D vision systems for robotics and security applications utilize object detection to perform video analysis in order to intelligently interact with their host environment and take appropriate actions. Such systems have high...
An adaptive, low-cost wear-leveling algorithm for multichannel solid-state disks
Li-Pin Chang, Tung-Yang Chou, Li-Chun Huang
Article No.: 55
Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. As flash memory endures only limited program-erase cycles, solid-state disks employ wear-leveling methods to prevent any...