Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS) - Regular Papers, Volume 13 Issue 4, November 2014

Section: Regular Papers

Abstracts: Online Supplements Volume 13, Number 1s Volume 13, Number 2s Volume 13, Number 3s Volume 13, Number 4s Volume 13, Number 5s

Article No.: 99
DOI: 10.1145/2688494.2688495

Editorial: Embedded everywhere for everyone
Sandeep K. Shukla
Article No.: 74
DOI: 10.1145/2559122

Rapid evaluation of custom instruction selection approaches with FPGA estimation
Siew-Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Article No.: 75
DOI: 10.1145/2560014

The main aim of this article is to demonstrate that a fast and accurate FPGA estimation engine is indispensable in design flows for custom instruction (template) selection. The need for a FPGA estimation engine stems from the difficulty in...

Task scheduling: A control-theoretical viewpoint for a general and flexible solution
Martina Maggio, Federico Terraneo, Alberto Leva
Article No.: 76
DOI: 10.1145/2560015

This article presents a new approach to the design of task scheduling algorithms, where system-theoretical methodologies are used throughout. The proposal implies a significant perspective shift with respect to mainstream design practices, but...

Elon: Enabling efficient and long-term reprogramming for wireless sensor networks
Wei Dong, Yunhao Liu, Chun Chen, Lin Gu, Xiaofan Wu
Article No.: 77
DOI: 10.1145/2560017

We present a new mechanism called Elon for enabling efficient and long-term reprogramming in wireless sensor networks. Elon reduces the transferred code size significantly by introducing the concept of replaceable component. It avoids the...

Bluetooth aided mobile phone localization: A nonlinear neural circuit approach
Shuai Li, Yuesheng Lou, Bo Liu
Article No.: 78
DOI: 10.1145/2560018

It is meaningful to design a strategy to roughly localize mobile phones without a GPS by exploiting existing conditions and devices especially in environments without GPS availability (e.g., tunnels, subway stations, etc.). The availability of...

Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors
Jingtong Hu, Qingfeng Zhuge, Chun Jason Xue, Wei-Che Tseng, Edwin H.-M. Sha
Article No.: 79
DOI: 10.1145/2560019

The recent emergence of various Non-Volatile Memories (NVMs), with many attractive characteristics such as low leakage power and high-density, provides us with a new way of addressing the memory power consumption problem. In this article, we...

Message blinding method requiring no multiplicative inversion for RSA
Heeseok Kim, Dong-Guk Han, Seokhie Hong, Jaecheol Ha
Article No.: 80
DOI: 10.1145/2560020

This article proposes a new message blinding methods requiring no multiplicative inversion for RSA. Most existing message blinding methods for RSA additionally require the multiplicative inversion, even though computational complexity of this...

A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation
Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici
Article No.: 81
DOI: 10.1145/2560031

Hardware-based parallel computing is proposed for acceleration of finite-element (FE) analysis of linear elastic deformation models. An implementation of the Preconditioned Conjugate Gradient algorithm on N Field Programmable Gate Array...

Building timing predictable embedded systems
Philip Axer, Rolf Ernst, Heiko Falk, Alain Girault, Daniel Grund, Nan Guan, Bengt Jonsson, Peter Marwedel, Jan Reineke, Christine Rochange, Maurice Sebastian, Reinhard Von Hanxleden, Reinhard Wilhelm, Wang Yi
Article No.: 82
DOI: 10.1145/2560033

A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the...

Embedded RAIDs-on-chip for bus-based chip-multiprocessors
Luis Angel D. Bathen, Nikil D. Dutt
Article No.: 83
DOI: 10.1145/2533316

The dual effects of larger die sizes and technology scaling, combined with aggressive voltage scaling for power reduction, increase the error rates for on-chip memories. Traditional on-chip memory reliability techniques (e.g., ECC) incur...

Python to accelerate embedded SoC design: A case study for systems biology
Evangelos Logaras, Orsalia G. Hazapis, Elias S. Manolakos
Article No.: 84
DOI: 10.1145/2560032

We present SysPy (System Python) a tool which exploits the strengths of the popular Python scripting language to boost design productivity of embedded System on Chips for FPGAs. SysPy acts as a “glue” software between...

A low-power instruction replay mechanism for design of resilient microprocessors
Rance Rodrigues, Arunachalam Annamalai, Sandip Kundu
Article No.: 85
DOI: 10.1145/2560034

There is a growing concern about the increasing rate of defects in computing substrates. Traditional redundancy solutions prove to be too expensive for commodity microprocessor systems. Modern microprocessors feature multiple execution units to...

Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system
Mohammad Khavari Tavana, Nasibeh Teimouri, Meisam Abdollahi, Maziar Goudarzi
Article No.: 86
DOI: 10.1145/2523781/2560035

Standby-sparing is one of the common techniques in order to design fault-tolerant safety-critical systems where the high level of reliability is needed. Recently, the minimization of energy consumption in embedded systems has attracted a lot of...

Towards scalable arithmetic units with graceful degradation
Danny P. Riemens, Georgi N. Gaydadjiev, Chris I. de Zeeuw, Christos Strydis
Article No.: 87
DOI: 10.1145/2499367

This article presents a new family of scalable arithmetic units (ScAUs) targeting resource-constrained, embedded devices. We, first, study the performance, power, area and scalability properties of general adders. Next, suitable error-detection...

Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer
Sung Kyu Park, Min Kyu Maeng, Ki-Woong Park, Kyu Ho Park
Article No.: 88
DOI: 10.1145/2558427

Phase Change RAM (PRAM) is a candidate to replace DRAM main memory due to its low idle power consumption and high scalability. However, its latency and endurance have generated problems in fulfilling its main memory role. The latency can be...

Transport triggered architecture to perform carrier synchronization for LTE
Omer Anjum, Mubashir Ali, Teemu Pitkänen, Jari Nurmi
Article No.: 89
DOI: 10.1145/2560036

In this article implementation of carrier frequency offset estimate for 20MHz LTE baseband processing is discussed. LTE (Long Term Evolution) is a wireless communication standard that makes use of some innovative techniques to gain very high data...

An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems
Juan Antonio Clemente, Javier Resano, Daniel Mozos
Article No.: 90
DOI: 10.1145/2560037

This article presents a methodology for building real-time reconfigurable systems that ensures that all the temporal constraints of a set of applications are met while optimizing the utilization of the available reconfigurable resources. Starting...

Bandwidth allocation for fixed-priority-scheduled compositional real-time systems
Farhana Dewan, Nathan Fisher
Article No.: 91
DOI: 10.1145/2560038

Recent research in compositional real-time systems has focused on determination of a component's real-time interface parameters. An important objective in interface-parameter determination is minimizing the bandwidth allocated to each component of...

Extended Instruction Exploration for Multiple-Issue Architectures
I-Wei Wu, Jean Jyh-Jiun Shann, Wei-Chung Hsu, Chung-Ping Chung
Article No.: 92
DOI: 10.1145/2560039

In order to satisfy the growing demand for high-performance computing in modern embedded devices, several architectural and microarchitectural enhancements have been implemented in processor architectures. Extended instruction (EI) is often used...

A study on parallelizing XML path filtering using accelerators
Roger Moussalli, Mariam Salloum, Robert Halstead, Walid Najjar, Vassilis J. Tsotras
Article No.: 93
DOI: 10.1145/2560040

Publish-subscribe systems present the state of the art in information dissemination to multiple users. Such systems have evolved from simple topic-based to the current XML-based systems. XML-based pub-sub systems provide users with more...

Providing reliable and real-time delivery in the presence of body shadowing in breadcrumb systems
Hengchang Liu, Pan Hui, Zhiheng Xie, Jingyuan Li, David Siu, Gang Zhou, Liusheng Huang, John A. Stankovic
Article No.: 94
DOI: 10.1145/2557633

The primary goal of breadcrumb trail sensor networks is to transmit in real-time users' physiological parameters that measure life-critical functions to an incident commander through reliable multihop communication. In applications using...

GPU-like on-chip system for decoding LDPC codes
Bertrand Le Gal, Christophe Jego
Article No.: 95
DOI: 10.1145/2538668

Rapid prototyping is an important step in the development and the verification of computationally demanding tasks of digital communication systems, such as Forward Error Correction (FEC) decoding. The goal is to replace time-consuming simulations...

Online learning of timeout policies for dynamic power management
Umair Ali Khan, Bernhard Rinner
Article No.: 96
DOI: 10.1145/2529992

Dynamic power management (DPM) refers to strategies which selectively change the operational states of a device during runtime to reduce the power consumption based on the past usage pattern, the current workload, and the given performance...

Simulation-based functional verification of dynamically reconfigurable systems
Lingkan Gong, Oliver Diessel
Article No.: 97
DOI: 10.1145/2560042

Dynamically reconfigurable systems (DRS) implemented using field-programmable gate arrays (FPGAs) allow hardware logic to be partially reconfigured while the rest of the design continues to operate. By mapping multiple reconfigurable hardware...

An asymmetric dual-processor architecture for low-power information appliances
François Guimbretiére, Shenwei Liu, Han Wang, Rajit Manohar
Article No.: 98
DOI: 10.1145/2560538

As users become increasingly conscious of their energy footprint—either to improve battery life or to respect the environment—improved energy efficiency of systems has gained in importance. This is especially important in the context...