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Editorial: Embedded systems -- more than methodology
Sandeep K. Shukla
Article No.: 99
Editorial: Special issue on design challenges for many-core processors
Masoud Daneshtalab, Maurizio Palesi, Juha Plosila
Article No.: 100
Towards a scalable, low-power all-optical architecture for networks-on-chip
Somayyeh Koohi, Yawei Yin, Shaahin Hessabi, S. J. Ben Yoo
Article No.: 101
This article proposes a scalable wavelength-routed optical Network on Chip (NoC) based on the Spidergon topology, named Power-efficient Scalable Wavelength-routed Network-on-chip (PeSWaN). The key idea of the proposed all-optical architecture is...
HARS: A hardware-assisted runtime software for embedded many-core architectures
Yves Lhuillier, Maroun Ojail, Alexandre Guerre, Jean-Marc Philippe, Karim Ben Chehida, Farhat Thabet, Caaliph Andriamisaina, Chafic Jaber, Raphaël David
Article No.: 102
The current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, cluster-based many-core accelerators with a shared hierarchical memory have emerged. Handling synchronizations on...
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches
Qiang Yang, Jian Fu, Raphael Poss, Chris Jesshope
Article No.: 103
When hardware cache coherence scales to many cores on chip, over saturated traffic of the shared memory system may offset the benefit from massive hardware concurrency. In this article, we investigate the cost of a write-update protocol in terms...
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality
Ritesh Parikh, Valeria Bertacco
Article No.: 104
As silicon technology scales, modern processor and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs. As a side effect of complexity of these designs, ensuring their correctness has...
Ultra-low-power adder stage design for exascale floating point units
Alberto A. Del Barrio, Nader Bagherzadeh, Román Hermida
Article No.: 105
Currently, the most powerful supercomputers can provide tens of petaflops. Future many-core systems are estimated to provide an exaflop. However, the power budget limitation makes these machines still unfeasible and unaffordable. Floating Point...
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
Yu-Jen Huang, Jin-Fu Li
Article No.: 106
A three-dimensional (3D) integrated circuit (IC) with multiple dies vertically connected by through-silicon-via (TSV) offers many benefits over current 2D ICs. Multicore logic-memory die stacking has been considered as one candidate for 3D ICs by...
Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs
Oliver Arnold, Emil Matus, Benedikt Noethen, Markus Winter, Torsten Limberg, Gerhard Fettweis
Article No.: 107
Heterogeneity and parallelism in MPSoCs for 4G (and beyond) communications signal processing are inevitable in order to meet stringent power constraints and performance requirements. The question arises on how to cope with the problem of system...
PAIS: Parallelism-aware interconnect scheduling in multicores
Yuho Jin, Timothy Mark Pinkston
Article No.: 108
Multicore processors have the potential to deliver scalable performance by distributing computation across multiple cores. However, the communication cost of parallel application thread execution may significantly limit the performance achievable...
UWB microwave imaging for breast cancer detection: Many-core, GPU, or FPGA?
Mario R. Casu, Francesco Colonna, Marco Crepaldi, Danilo Demarchi, Mariagrazia Graziano, Maurizio Zamboni
Article No.: 109
An UWB microwave imaging system for breast cancer detection consists of antennas, transceivers, and a high-performance embedded system for elaborating the received signals and reconstructing breast images. In this article we focus on this embedded...
Energy optimization for real-time multiprocessor system-on-chip with optimal DVFS and DPM combination
Gang Chen, Kai Huang, Alois Knoll
Article No.: 111
Energy optimization is a critical design concern for embedded systems. Combining D
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
Rawan Abdel-Khalek, Valeria Bertacco
Article No.: 112
The increasing number of units in today's systems-on-chip and multicore processors has led to complex intra-chip communication solutions. Specifically, Networks-on-Chip (NoCs) have emerged as a favorable fabric to provide high bandwidth and low...
NoC contention analysis using a branch-and-prune algorithm
Dakshina Dasari, Borislav Nikoli'c, Vincent N'elis, Stefan M. Petters
Article No.: 113
“Many-core” systems based on a Network-on-Chip (NoC) architecture offer various opportunities in terms of performance and computing capabilities, but at the same time they pose many challenges for the deployment of real-time systems,...
HARP: Harnessing inactive threads in many-core processors
Ahmad Lashgar, Ahmad Khonsari, Amirali Baniasadi
Article No.: 114
SIMT accelerators are equipped with thousands of computational resources. Conventional accelerators, however, fail to fully utilize available resources due to branch and memory divergences. This underutilization is manifested in two underlying...
NoC-based fault-tolerant cache design in chip multiprocessors
Abbas Banaiyanmofrad, Gustavo Girão, Nikil Dutt
Article No.: 115
Advances in technology scaling increasingly make emerging Chip MultiProcessor (CMP) platforms more susceptible to failures that cause various reliability challenges. In such platforms, error-prone on-chip memories (caches) continue to dominate the...
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
Shirish Bahirat, Sudeep Pasricha
Article No.: 116
With increasing application complexity and improvements in process technology, Chip MultiProcessors (CMPs) with tens to hundreds of cores on a chip are becoming a reality. Networks-on-Chip (NoCs) have emerged as scalable communication fabrics that...
Exploiting replication to improve performances of NUCA-based CMP systems
Pierfrancesco Foglia, Marco Solinas
Article No.: 117
Improvements in semiconductor nanotechnology made chip multiprocessors the reference architecture for high-performance microprocessors. CMPs usually adopt large Last-Level Caches (LLC) shared among cores and private L1 caches, whose performances...