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ACM Transactions on Embedded Computing Systems (TECS), Volume 14 Issue 2, March 2015

Editorial: Oh Security—Where Art Thou?
Sandeep K. Shukla
Article No.: 20
DOI: 10.1145/2742044

Stability of Online Resource Managers for Distributed Systems under Execution Time Variations
Sergiu Rafiliu, Petru Eles, Zebo Peng, Michael Lemmon
Article No.: 21
DOI: 10.1145/2629495

Today's embedded systems are exposed to variations in resource usage due to complex software applications, hardware platforms, and impact of the runtime environments. When these variations are large and efficiency is required, on-line resource...

Mobile Computations with Surrounding Devices: Proximity Sensing and MultiLayered Work Stealing
Seng W. Loke, Keegan Napier, Abdulaziz Alali, Niroshinie Fernando, Wenny Rahayu
Article No.: 22
DOI: 10.1145/2656214

With the proliferation of mobile devices, and their increasingly powerful embedded processors and storage, vast resources increasingly surround users. We have been investigating the concept of on-demand ad hoc forming of groups of nearby mobile...

Heuristics on Reachability Trees for Bicriteria Scheduling of Stream Graphs on Heterogeneous Multiprocessor Architectures
Avinash Malik, David Gregg
Article No.: 23
DOI: 10.1145/2638553

In this article, we partition and schedule Synchronous Dataflow (SDF) graphs onto heterogeneous execution architectures in such a way as to minimize energy consumption and maximize throughput. Partitioning and scheduling SDF graphs onto...

Runtime Optimization of System Utility with Variable Hardware
Paul Martin, Lucas Wanner, Mani Srivastava
Article No.: 24
DOI: 10.1145/2656338

Increasing hardware variability in newer integrated circuit fabrication technologies has caused corresponding power variations on a large scale. These variations are particularly exaggerated for idle power consumption, motivating the need to...

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels
Manil Dev Gomony, Benny Akesson, Kees Goossens
Article No.: 25
DOI: 10.1145/2661635

Ever-increasing demands for main memory bandwidth and memory speed/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource in...

Factored Planning: From Automata to Petri Nets
Loïg Jezequel, Eric Fabre, Victor Khomenko
Article No.: 26
DOI: 10.1145/2656215

Factored planning mitigates the state explosion problem by avoiding the construction of the state space of the whole system and instead working with the system's components. Traditionally, finite automata have been used to represent the...

Automatic Update of Indoor Location Fingerprints with Pedestrian Dead Reckoning
Daisuke Taniuchi, Takuya Maekawa
Article No.: 27
DOI: 10.1145/2667226

In this article, we propose a new method for automatically updating a Wi-Fi indoor positioning model on a cloud server by employing uploaded sensor data obtained from the smartphone sensors of a specific user who spends a lot of time in a given...

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash
Xavier Jimenez, David Novo, Paolo Ienne
Article No.: 28
DOI: 10.1145/2638552

Hybrid flash storages combine a small Single-Level Cell (SLC) partition with a large Multilevel Cell (MLC) partition. Compared to MLC-only solutions, the SLC partition exploits fast and short local write updates, while the MLC part...

Plugging Versus Logging: Adaptive Buffer Management for Hybrid-Mapping SSDs
Li-Pin Chang, Yo-Chuan Su, I-Chen Wu
Article No.: 29
DOI: 10.1145/2629455

A promising technique to improve the write performance of solid-state disks (SSDs) is to use a disk write buffer. The goals of a write buffer is not only to reduce the write traffic to the flash chips but also to convert host write patterns into...

Temperature-Aware Data Allocation for Embedded Systems with Cache and Scratchpad Memory
Zhiping Jia, Yang Li, Yi Wang, Meng Wang, Zili Shao
Article No.: 30
DOI: 10.1145/2629650

The hybrid memory architecture that contains both on-chip cache and scratchpad memory (SPM) has been widely used in embedded systems. In this article, we explore this hybrid memory architecture by jointly optimizing time performance and...

Multilevel Phase Analysis
Weihua Zhang, Jiaxin Li, Yi Li, Haibo Chen
Article No.: 31
DOI: 10.1145/2629594

Phase analysis, which classifies the set of execution intervals with similar execution behavior and resource requirements, has been widely used in a variety of systems, including dynamic cache reconfiguration, prefetching, race detection, and...

Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation
Abbas Banaiyanmofrad, Houman Homayoun, Nikil Dutt
Article No.: 32
DOI: 10.1145/2629566

Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation--induced...

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs
Muhsen Owaida, Gabriel Falcao, Joao Andrade, Christos Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
Article No.: 33
DOI: 10.1145/2656207

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI...

Towards Write-Activity-Aware Page Table Management for Non-volatile Main Memories
Tianzheng Wang, Duo Liu, Yi Wang, Zili Shao
Article No.: 34
DOI: 10.1145/2697394

Non-volatile memories such as phase change memory (PCM) and memristor are being actively studied as an alternative to DRAM-based main memory in embedded systems because of their properties, which include low power consumption and high density....

A Java Processor IP Design for Embedded SoC
Chun-Jen Tsai, Han-Wen Kuo, Zigang Lin, Zi-Jing Guo, Jun-Fu Wang
Article No.: 35
DOI: 10.1145/2629649

In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a...

A Hardware-Efficient Architecture for Accurate Real-Time Disparity Map Estimation
Christos Ttofis, Christos Kyrkou, Theocharis Theocharides
Article No.: 36
DOI: 10.1145/2629699

Emerging embedded vision systems utilize disparity estimation as a means to perceive depth information to intelligently interact with their host environment and take appropriate actions. Such systems demand high processing performance and accurate...

Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems
Miguel Peón-quirós, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, José Manuel Mendías, Dimitrios Soudris
Article No.: 37
DOI: 10.1145/2656208

Software applications use dynamic memory (allocated and deallocated in the system's heap) to handle dynamism in their working conditions. Embedded systems tend to include complex memory organizations but most techniques for dynamic memory...

ACDC: Small, Predictable and High-Performance Data Cache
Juan Segarra, Clemente Rodríguez, Rubén Gran, Luis C. Aparicio, Víctor Viñals
Article No.: 38
DOI: 10.1145/2677093

In multitasking real-time systems, the worst-case execution time (WCET) of each task and also the effects of interferences between tasks in the worst-case scenario need to be calculated. This is especially complex in the presence of data caches....

Effective Runtime Resource Management Using Linux Control Groups with the BarbequeRTRM Framework
Patrick Bellasi, Giuseppe Massari, William Fornaciari
Article No.: 39
DOI: 10.1145/2658990

The extremely high technology process reached by silicon manufacturing (smaller than 32nm) has led to production of computational platforms and SoC, featuring a considerable amount of resources. Whereas from one side such multi- and many-core...