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Editorial: Schizoid Design for Critical Embedded Systems
Sandeep K. Shukla
Article No.: 40e
Introduction for Embedded Platforms for Cryptography in the Coming Decade
Patrick Schaumont, Maire O'Neill, Tim Güneysu
Article No.: 40
Digital signatures are an important primitive for building secure systems and are used in most real-world security protocols. However, almost all popular signature schemes are either based on the factoring assumption (RSA) or the hardness of the...
On Constrained Implementation of Lattice-Based Cryptographic Primitives and Schemes on Smart Cards
Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili
Article No.: 42
Most lattice-based cryptographic schemes with a security proof suffer from large key sizes and heavy computations. This is also true for the simpler case of authentication protocols that are used on smart cards as a very-constrained computing...
The Future of Real-Time Security: Latency-Optimized Lattice-Based Digital Signatures
Aydin Aysu, Bilgiday Yuce, Patrick Schaumont
Article No.: 43
Advances in quantum computing have spurred a significant amount of research into public-key cryptographic algorithms that are resistant against postquantum cryptanalysis. Lattice-based cryptography is one of the important candidates because of its...
With respect to performance, asymmetric code-based cryptography based on binary Goppa codes has been reported as a highly interesting alternative to RSA and ECC. A major drawback is still the large keys in the range between 50 and 100KB that...
Optimized and Scalable Co-Processor for McEliece with Binary Goppa Codes
Pedro Maat C. Massolino, Paulo S. L. M. Barreto, Wilson V. Ruggiero
Article No.: 45
Asymmetric cryptographic primitives are essential to enable secure communications in public networks or public mediums. Such primitives can be deployed as software libraries or hardware co-processors, the latter being more commonly employed in...
Section: Special Issue on Embedded Platforms for Crypto
Modeling and Analyzing Dataflow Applications on NoC-Based Many-Core Architectures
Jean-Vivien Millo, Emilien Kofman, Robert De Simone
Article No.: 46
The advent of chip-level parallel architectures prompted a renewal of interest into dataflow process networks. The trend is to model an application independently from the architecture, then the model is morphed to best fit the target architecture....
Global and Partitioned Multiprocessor Fixed Priority Scheduling with Deferred Preemption
Robert I. Davis, Alan Burns, Jose Marinho, Vincent Nelis, Stefan M. Petters, Marko Bertogna
Article No.: 47
This article introduces schedulability analysis for Global Fixed Priority Scheduling with Deferred Preemption (gFPDS) for homogeneous multiprocessor systems. gFPDS is a superset of Global Fixed Priority Preemptive Scheduling (gFPPS) and Global...
Guaranteed Computational Resprinting via Model-Predictive Control
Andrea Tilli, Andrea Bartolini, Matteo Cacciari, Luca Benini
Article No.: 48
Today and future many-core systems are facing the utilization wall and dark silicon problems, for which not all the processing engines can be powered at the same time as this will lead to a power consumption higher than the Total...
Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications
Parinaz Sayyah, Mihai T. Lazarescu, Sara Bocchio, Emad Ebeid, Gianluca Palermo, Davide Quaglia, Alberto Rosti, Luciano Lavagno
Article No.: 49
Networked embedded systems are essential building blocks of a broad variety of distributed applications ranging from agriculture to industrial automation to healthcare and more. These often require specific energy optimizations to increase the...
Design Optimization of Mixed-Criticality Real-Time Embedded Systems
Domiţian Tămaş-Selicean, Paul Pop
Article No.: 50
In this article, we are interested in implementing mixed-criticality real-time embedded applications on a given heterogeneous distributed architecture. Applications have different criticality levels, captured by their Safety-Integrity Level (SIL),...
Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems
Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Article No.: 51
Embedded systems are becoming increasingly common in everyday life and like their general-purpose counterparts, they have shifted towards shared memory multicore architectures. However, they are much more resource constrained, and as they often...
A Probabilistic Calculus for Probabilistic Real-Time Systems
Luca Santinelli, Liliana Cucu-Grosjean
Article No.: 52
Challenges within real-time research are mostly in terms of modeling and analyzing the complexity of actual real-time embedded systems. Probabilities are effective in both modeling and analyzing embedded systems by increasing the amount of...
Instruction-Cache Locking for Improving Embedded Systems Performance
Kapil Anand, Rajeev Barua
Article No.: 53
Cache memories in embedded systems play an important role in reducing the execution time of applications. Various kinds of extensions have been added to cache hardware to enable software involvement in replacement decisions, improving the runtime...
Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application Portability
Patrick Cooke, Lu Hao, Greg Stitt
Article No.: 54
Despite significant advantages, wider usage of field-programmable gate arrays (FPGAs) has been limited by lengthy compilation and a lack of portability. Virtual-architecture overlays have partially addressed these problems, but previous work...
Using Network Traffic to Infer Hardware State: A Kernel-Level Investigation
Lanier Watkins, William H. Robinson, Raheem Beyah
Article No.: 55
In this article, we illustrate that the boundary of a general-purpose node can be extended into the network by extracting information from network traffic generated by that general-purpose node to infer the state of its hardware components. This...
Energy Modeling of Software for a Hardware Multithreaded Embedded Microprocessor
Steve Kerrison, Kerstin Eder
Article No.: 56
This article examines a hardware multithreaded microprocessor and discusses the impact such an architecture has on existing software energy modeling techniques. A framework is constructed for analyzing the energy behavior of the XMOS XS1-L...
Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Article No.: 57
Multiprocessor Systems-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection topologies potentially meeting given communication requirements, determining various trade-offs between cost and performance. Building...
On the Verification of Concurrent, Asynchronous Programs with Waiting Queues
Gilles Geeraerts, Alexander Heußner, Jean-François Raskin
Article No.: 58
Recently, new libraries, such as Grand Central Dispatch (GCD), have been proposed to directly harness the power of multicore platforms and to make the development of concurrent software more accessible to software engineers. When using such a...
Communication Optimizations for Multithreaded Code Generation from Simulink Models
Kai Huang, Min Yu, Rongjie Yan, Xiaomeng Zhang, Xiaolang Yan, Lisane Brisolara, Ahmed Amine Jerraya, Jiong Feng
Article No.: 59
Communication frequency is increasing with the growing complexity of emerging embedded applications and the number of processors in the implemented multiprocessor SoC architectures. In this article, we consider the issue of communication cost...
Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as...