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ACM Transactions on Embedded Computing Systems (TECS), Volume 14 Issue 4, December 2015



Section: Special Issue on Application of Concurrency to System Design

Editorial: Big Data, Internet of Things, Cybersecurity—A New Trinity of Embedded Systems Research
Sandeep K. Shukla
Article No.: 61
DOI: 10.1145/2820608

Guest Editorial for Special Issue Application of Concurrency to System Design
Kamel Barkaoui, Luca Bernardinello, Andrey Mokhov
Article No.: 62
DOI: 10.1145/2809925

Memory-Model-Aware Testing: A Unified Complexity Analysis
Florian Furbach, Roland Meyer, Klaus Schneider, Maximilian Senftleben
Article No.: 63
DOI: 10.1145/2753761

To improve the performance of the memory system, multiprocessors implement weak memory consistency models. Weak memory models admit different views of the processes on their load and store instructions, thus allowing for computations that are not...

Action Synthesis for Branching Time Logic: Theory and Applications
Michał Knapik, Artur Męski, Wojciech Penczek
Article No.: 64
DOI: 10.1145/2746337

The article introduces a parametric extension of Action-Restricted Computation Tree Logic called pmARCTL. A symbolic fixed-point algorithm providing a solution to the exhaustive parameter synthesis problem is proposed. The parametric approach...

Parametrised Modal Interface Automata
Antti Siirtola, Keijo Heljanko
Article No.: 65
DOI: 10.1145/2776892

Interface theories (ITs) enable us to analyse the compatibility interfaces and refine them while preserving their compatibility. However, most ITs are for finite state interfaces, whereas computing systems are often parametrised involving...

STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems
Sylvain Cotard, Audrey Queudet, Jean-Luc Béchennec, Sébastien Faucou, Yvon Trinquet
Article No.: 66
DOI: 10.1145/2786979

This article introduces STM-HRT, a nonblocking wait-free software transactional memory (STM) for hard real-time (HRT) multicore embedded systems. Resource access control in HRT systems is usually implemented with lock-based synchronization....

Failure Semantics for Modal Transition Systems
Ferenc Bujtor, Walter Vogler
Article No.: 67
DOI: 10.1145/2746336

With the aim to preserve deadlock freedom, we define a new refinement preorder for modal transition systems (MTSs), using an MTS-specific variant of testing inspired by De Nicola and Hennessy. We characterize this refinement with a kind of failure...

Incremental Analysis of Cyclo-Static Synchronous Dataflow Graphs
Robert De Groote, Philip K. F. Hölzenspies, Jan Kuper, Gerard J. M. Smit
Article No.: 68
DOI: 10.1145/2792981

In this article, we present a mathematical characterisation of admissible schedules of cyclo-static dataflow (csdf) graphs. We demonstrate how algebra ic manipulation of this characterization is related to unfolding csdf...

Diagnosability under Weak Fairness
Vasileios Germanos, Stefan Haar, Victor Khomenko, Stefan Schwoon
Article No.: 69
DOI: 10.1145/2832910

In partially observed Petri nets, diagnosis is the task of detecting whether the given sequence of observed labels indicates that some unobservable fault has occurred. Diagnosability is an associated property of the Petri net, stating that in any...

Section: Special Issue on Application of Concurrency to System Design

Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors
Gung-Yu Pan, Jed Yang, Jing-Yang Jou, Bo-Cheng Charles Lai
Article No.: 70
DOI: 10.1145/2811404

Multiprocessors have become the main architecture trend in modern systems due to the superior performance; nevertheless, the power consumption remains a critical challenge. Global power management (GPM) aims at dynamically finding the power state...

Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores
Jing Lu, Ke Bai, Aviral Shrivastava
Article No.: 71
DOI: 10.1145/2738039

Scaling the memory hierarchy is a major challenge when we scale the number of cores in a multicore processor. Software Managed Multicore (SMM) architectures come up as one of the promising solutions. In an SMM architecture, there are no caches,...

OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs
Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram
Article No.: 72
DOI: 10.1145/2764458

In this article, a heuristic custom instruction (CI) selection algorithm is presented. The proposed algorithm, which is called OPLE for “Optimization based on Partitioning and Local Exploration,” uses a combination of greedy and...

3D CV Descriptor on Parallel Heterogeneous Platforms
Daniele Palossi, Martino Ruggiero, Luca Benini
Article No.: 73
DOI: 10.1145/2733377

Embedded three-dimensional (3D) Computer Vision (CV) is considered a technology enabler for future consumer applications, attracting a wide interest in academia and industry. However, 3D CV processing is a computation-intensive task. Its high...

Crenel-Interval-Based Dynamic Power Management for Periodic Real-Time Systems
Guohui Li, Yi Zhang, Jianjun Li
Article No.: 74
DOI: 10.1145/2744197

In order to save the energy consumption of real-time embedded systems, the integration of Dynamic Voltage and Frequency Scaling (DVFS) and Device Power Management (DPM) techniques has been well studied. In this article, we propose a new energy...

Architecture-Aware Real-Time Compression of Execution Traces
Bojan Mihajlović, Željko Žilić, Warren J. Gross
Article No.: 75
DOI: 10.1145/2766449

In recent years, on-chip trace generation has been recognized as a solution to the debugging of increasingly complex software. An execution trace can be seen as the most fundamentally useful type of trace, allowing the execution path of...

Safety and Progress for Distributed Cyber-Physical Systems with Unreliable Communication
Stanley Bak, Zhenqi Huang, Fardin Abdi Taghi Abad, Marco Caccamo
Article No.: 76
DOI: 10.1145/2739046

Cyber-physical systems (CPSs) may interact and manipulate objects in the physical world, and therefore formal guarantees about their behavior are strongly desired. Static-time proofs of safety invariants, however, may be intractable for systems...

Parameter Space Representation of Pareto Front to Explore Hardware-Software Dependencies
Vincenzo Catania, Andrea Araldo, Davide Patti
Article No.: 77
DOI: 10.1145/2764457

Embedded systems design requires conflicting objectives to be optimized with an appropriate choice of hardware-software parameters. A simulation campaign can guide the design in finding the best trade-offs, but due to the big number of possible...

Perpetuu: A Tiered Solar-powered GIS Microserver
Adam Matthews, Stanislav Bobovych, Nilanjan Banerjee, James P. Parkerson, Ryan Robucci, Chintan Patel
Article No.: 78
DOI: 10.1145/2767128

The aftermath of a natural disaster is characterized by lack of a reliable medium for dissemination of information to survivors. The state-of-the-art emergency response systems rely on satellite radio-enabled devices, but survivors, unlike first...

Runtime Monitoring of Cyber-Physical Systems Under Timing and Memory Constraints
Ramy Medhat, Borzoo Bonakdarpour, Deepak Kumar, Sebastian Fischmeister
Article No.: 79
DOI: 10.1145/2744196

The goal of runtime monitoring is to inspect the well-being of a system by employing a monitor process that reads the state of the system during execution and evaluates a set of properties expressed in some specification language....

A Sliding Window Phase-Only Correlation Method for Side-Channel Alignment in a Smartphone
Catherine H. Gebotys, Brian A. White
Article No.: 80
DOI: 10.1145/2783441

Future wireless embedded devices will be increasingly powerful, supporting many more applications including one of the most crucial, security. Although many embedded devices offer resistance to bus probing attacks due to their compact size and...

Resource Synchronization and Preemption Thresholds Within Mixed-Criticality Scheduling
Qingling Zhao, Zonghua Gu, Haibo Zeng
Article No.: 81
DOI: 10.1145/2783440

In a mixed-criticality system, multiple tasks with different levels of criticality may coexist on the same hardware platform. The scheduling algorithm EDF-VD (Earliest Deadline First with Virtual Deadlines) has been proposed for mixed-criticality...

A Storage Device Emulator for System Performance Evaluation
Ming-Ju Wu, Chun-Jen Tsai
Article No.: 82
DOI: 10.1145/2785969

The performance and characteristics of the storage devices used in embedded systems can have a great influence on the overall end user experience. When building embedded systems or designing new storage device components, it is important for the...

Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process Variation
Davit Mirzoyan, Benny Akesson, Sander Stuijk, Kees Goossens
Article No.: 83
DOI: 10.1145/2785968

Scaling CMOS technology into nanometer feature-size nodes has made it practically impossible to precisely control the manufacturing process. This results in variation in the speed and power consumption of a circuit. As a solution to...

Cooperative Data Reduction in Wireless Sensor Network
Shiwen Zhang, Qingquan Zhang, Sheng Xiao, Ting Zhu, Yu Gu, Yaping Lin
Article No.: 84
DOI: 10.1145/2786755

In wireless sensor networks, owing to the limited energy of the sensor node, it is very meaningful to propose a dynamic scheduling scheme with data management that reduces energy as soon as possible. However, traditional techniques treat data...

Anonymous Split E-Cash—Toward Mobile Anonymous Payments
Marijn Scheir, Josep Balasch, Alfredo Rial, Bart Preneel, Ingrid Verbauwhede
Article No.: 85
DOI: 10.1145/2783439

Anonymous E-Cash was first introduced in 1982 as a digital, privacy-preserving alternative to physical cash. A lot of research has since then been devoted to extend and improve its properties, leading to the appearance of multiple schemes. Despite...

Analyzing Event-Based Scheduling in Concurrent Reactive Systems
Jian-Min Jiang, Huibiao Zhu, Qin Li, Yongxin Zhao, Lin Zhao, Shi Zhang, Ping Gong, Zhong Hong
Article No.: 86
DOI: 10.1145/2783438

The traditional research on scheduling focuses on task scheduling and schedulability analysis in concurrent reactive systems. In this article, we dedicate ourselves to event-based scheduling. We first formally define an event-based scheduling...