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ACM Transactions on Embedded Computing Systems (TECS), Volume 15 Issue 3, July 2016

Editorial: Fence Itself Grazing the Field—Security from the Sentries
Sandeep K. Shukla
Article No.: 41e
DOI: 10.1145/2953045

Bandwidth Optimization and Energy Management in Real-Time Wireless Networks
Gianluca Franchino, Giorgio Buttazzo, Mauro Marinoni
Article No.: 41
DOI: 10.1145/2851498

In embedded systems operated by battery and interacting with the environment, a fundamental issue is the enforcement of real-time and energy constraints to guarantee a desired lifetime with a given performance. A lot of research has focused on...

UPDATE: User-Profile-Driven Adaptive TransfEr for Mobile Devices
Yichuan Wang, Xin Liu, Cheng-Hsin Hsu
Article No.: 42
DOI: 10.1145/2889489

Existing channel-aware scheduling work has mainly focused on scheduling in small timescales, that is, tens to hundreds of seconds. We propose to use long-term user profiles to provide useful statistical information on future network conditions in...

An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
Article No.: 43
DOI: 10.1145/2866578

The recent advent of many-accelerator systems-on-chip (SoC), driven by the need for maximizing throughput and power efficiency, has led to an exponential increase in the hardware/software co-design complexity. The reason of this increase is that...

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices
Ivan Beretta, Vincenzo Rana, Abdulkadir Akin, Alessandro Antonio Nacci, Donatella Sciuto, David Atienza
Article No.: 44
DOI: 10.1145/2851497

The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as graphics processing units (GPUs) or field-programmable gate arrays (FPGAs), which are often...

Fast and Precise Worst-Case Interference Placement for Shared Cache Analysis
Kartik Nagar, Y. N. Srikant
Article No.: 45
DOI: 10.1145/2854151

Real-time systems require a safe and precise estimate of the worst-case execution time (WCET) of programs. In multicore architectures, the precision of a program’s WCET estimate highly depends on the precision of its predicted shared cache...

Evaluating the Design of a VLIW Processor for Real-Time Systems
Renan Augusto Starke, Andreu Carminati, Rômulo Silva De Oliveira
Article No.: 46
DOI: 10.1145/2889490

Nowadays, many real-time applications are very complex and as the complexity and the requirements of those systems become more demanding, more hardware processing capacity is necessary. Unfortunately, the correct functioning of real-time systems...

SmartLMK: A Memory Reclamation Scheme for Improving User-Perceived App Launch Time
Sang-Hoon Kim, Jinkyu Jeong, Jin-Soo Kim, Seungryoul Maeng
Article No.: 47
DOI: 10.1145/2894755

As the mobile computing environment evolves, users demand high-quality apps and better user experience. Consequently, memory demand in mobile devices has soared. Device manufacturers have fulfilled the demand by equipping devices with more RAM....

Accurate Prediction of Available Battery Time for Mobile Applications
Dongwon Kim, Yohan Chon, Wonwoo Jung, Yungeun Kim, Hojung Cha
Article No.: 48
DOI: 10.1145/2875423

Energy consumption in mobile devices is an important issue for both system developers and users. Users are aware of the battery-related information of their mobile devices and tend to take appropriate actions to increase the battery life. In this...

Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks Under Fluid Scheduling Model
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
Article No.: 49
DOI: 10.1145/2883612

With the growing need to address the thermal issues in modern processing platforms, various performance throttling schemes have been proposed in literature (DVFS, clock gating, and so on) to manage temperature. In real-time systems, such methods...

Usage-Specific Semantic Integration for Cyber-Physical Robot Systems
Fang Li, Jiafu Wan, Ping Zhang, Di Li, Daqiang Zhang, Keliang Zhou
Article No.: 50
DOI: 10.1145/2873057

The multidisciplinary nature and time criticality of computing in Cyber-Physical Robot Systems (CPRS) makes it significantly different from traditional computer systems. This article attempts to create a usage-specific language called...

Model-Based Design of Correct Controllers for Dynamically Reconfigurable Architectures
Xin An, Eric Rutten, Jean-Philippe Diguet, Abdoulaye Gamatié
Article No.: 51
DOI: 10.1145/2873056

Dynamically reconfigurable hardware has been identified as a promising solution for the design of energy-efficient embedded systems. However, its adoption is limited by costly design effort, including verification and validation, which is even...

A Collaborative Energy-Aware Sensor Management System Using Team Theory
Allaa R. Hilal, Otman Basir
Article No.: 52
DOI: 10.1145/2910574

With limited battery supply, power is a scarce commodity in wireless sensor networks. Thus, to prolong the lifetime of the network, it is imperative that the sensor resources are managed effectively. This task is particularly challenging in...

Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore
Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernandez, Francisco Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka
Article No.: 53
DOI: 10.1145/2910589

The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A...

Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay
Bogdan Tanasa, Unmesh D. Bordoloi, Petru Eles, Zebo Peng
Article No.: 54
DOI: 10.1145/2870635

We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratio of each message. The core problem is...

Byte-Addressable Update Scheme to Minimize the Energy Consumption of PCM-Based Storage Systems
Ming-Chang Yang, Yuan-Hao Chang, Che-Wei Tsao
Article No.: 55
DOI: 10.1145/2910590

In recent years, phase-change memory (PCM) has generated a great deal of interest because of its byte addressability and nonvolatility properties. It is regarded as a good alternative storage medium that can reduce the performance gap between the...

Evaluation and Improvements of Runtime Monitoring Methods for Real-Time Event Streams
Biao Hu, Kai Huang, Gang Chen, Long Cheng, Alois Knoll
Article No.: 56
DOI: 10.1145/2890503

Runtime monitoring is of great importance as a safeguard to guarantee the correctness of system runtime behaviors. Two state-of-the-art methods, dynamic counters and l-repetitive function, were recently developed to tackle the runtime...

Vector Coprocessor Virtualization for Simultaneous Multithreading
Yaojie Lu, Seyedamin Rooholamin, Sotirios G. Ziavras
Article No.: 57
DOI: 10.1145/2898364

Vector coprocessors (VPs), commonly being assigned exclusively to a single thread/core, are not often performance and energy efficient due to mismatches with the vector needs of individual applications. We present in this article an...

Hybrid Montgomery Reduction
Hwajeong Seo, Zhe Liu, Yasuyuki Nogami, Jongseok Choi, Howon Kim
Article No.: 58
DOI: 10.1145/2890502

In this article, we present a hybrid method to improve the performance of the Montgomery reduction by taking advantage of the Karatsuba technique. We divide the Montgomery reduction into two sub-parts, including one for the conventional Montgomery...

Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures
Iason Filippopoulos, Namita Sharma, Francky Catthoor, Per Gunnar Kjeldsberg, Preeti Ranjan Panda
Article No.: 59
DOI: 10.1145/2894754

This work presents a methodology for efficient exploration of data interleaving and data-to-memory mapping options for Single Instruction Multiple Data (SIMD) platform architectures. The system architecture consists of a reconfigurable clustered...

Live-Out Register Fencing: Interrupt-Triggered Soft Error Correction Based on the Elimination of Register-to-Register Communication
Ronaldo R. Ferreira, Gabriel L. Nazar, Jean Da Rolt, Álvaro F. Moreira, Luigi Carro
Article No.: 60
DOI: 10.1145/2873058

This article introduces Live-Out Register Fencing (LoRF), a soft error correction mechanism that uses the novel Spill Register File as a container of checkpointing data. LoRF’s Spill Register File holds the values shared among basic...

RunStream: A High-Level Rapid Prototyping Framework for Stream Ciphers
Ayesha Khalid, Goutam Paul, Anupam Chattopadhyay, Faezeh Abediostad, Syed Imad Ud Din, Muhammad Hassan, Baishik Biswas, Prasanna Ravi
Article No.: 61
DOI: 10.1145/2891412

We present RunStream, a rapid prototyping framework for realizing stream cipher implementations based on algorithmic specifications and architectural customizations desired by the users. In the dynamic world of cryptography where newer...