Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS), Volume 16 Issue 4, July 2017

Section: Special Issue on Secure and Fault-Tolerant Embedded Computing

Guest Editorial: Special Issue on “Secure and Fault-Tolerant Embedded Computing”
Dr. Jimson Mathew, Dr. Rajat Subhra Chakraborty, Prof. Dhiraj K. Pradhan
Article No.: 92
DOI: 10.1145/3075563

Protecting Caches from Soft Errors: A Microarchitect’s Perspective
Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava
Article No.: 93
DOI: 10.1145/3063180

Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error...

A Novel Method for Online Detection of Faults Affecting Execution-Time in Multicore-Based Systems
Stefano Esposito, Massimo Violante, Marco Sozzi, Marco Terrone, Massimo Traversone
Article No.: 94
DOI: 10.1145/3063313

This article proposes a bounded interference method, based on statistical evaluations, for online detection and tolerance of any fault capable of causing a deadline miss. The proposed method requires data that can be gathered during the profiling...

Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression
Maria Isabel Mera, Jonah Caplan, Seyyed Hasan Mozafari, Brett H. Meyer, Peter Milder
Article No.: 96
DOI: 10.1145/3063312

An emerging trend in safety-critical computer system design is the use of compression—for example, using cyclic redundancy check (CRC) or Fletcher checksum (FC)—to reduce the state that must be compared to verify correct redundant...

Section: Special Issue on Secure and Fault-Tolerant Embedded Computing

Formal Model-Based Synthesis of Application-Specific Static RTOS
Kabland Toussaint Gautier Tigori, Jean-Luc Béchennec, Sébastien Faucou, Olivier Henri Roux
Article No.: 97
DOI: 10.1145/3015777

In an embedded system, the specialization of the code of the real-time operating system (RTOS) according to the requirements of the application allows one to remove unused services and other sources of dead code from the binary program. The...

The Design and Implementation of the Synchronous Language CÉU
Francisco Sant'anna, Roberto Ierusalimschy, Noemi Rodriguez, Silvana Rossetto, Adriano Branco
Article No.: 98
DOI: 10.1145/3035544

CéU is a synchronous language targeting soft real-time systems. It is inspired by Esterel and has a simple semantics with fine-grain control over program execution. CéU uses an event-triggered notion of time...

The Perfect Getaway: Using Escape Analysis in Embedded Real-Time Systems
Isabella Stilkerich, Clemens Lang, Christoph Erhardt, Christian Bay, Michael Stilkerich
Article No.: 99
DOI: 10.1145/3035542

The use of a managed, type-safe language such as Java in real-time and embedded systems offers productivity and, in particular, safety and dependability benefits at a reasonable cost. It has been shown for commodity systems that Escape Analysis...

PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems
Mohamed Hassan, Hiren Patel, Rodolfo Pellizzoni
Article No.: 100
DOI: 10.1145/3019611

We propose a novel approach to schedule memory requests in Mixed Criticality Systems (MCS). This approach supports an arbitrary number of criticality levels by enabling the MCS designer to specify memory requirements per task. It retains locality...

Refining Cache Behavior Prediction Using Cache Miss Paths
Kartik Nagar, Y. N. Srikant
Article No.: 103
DOI: 10.1145/3035541

Worst-Case Execution Time (WCET) is an important metric for programs running on real-time systems, and finding precise estimates of a program’s WCET is crucial to avoid wastage of hardware resources and to improve the schedulability of task...

Automatic Synthesis of Switching Controllers for Linear Hybrid Systems: Reachability Control
Massimo Benerecetti, Marco Faella
Article No.: 104
DOI: 10.1145/3047500

We consider the problem of computing the controllable region of a Linear Hybrid Automaton with controllable and uncontrollable transitions, w.r.t. a reachability objective. We provide an algorithm for the finite-horizon version of the problem,...

Task Transition Scheduling for Data-Adaptable Systems
Nathan Sandoval, Casey Mackin, Sean Whitsitt, Vijay Shankar Gopinath, Sachidanand Mahadevan, Andrew Milakovich, Kyle Merry, Jonathan Sprinkle, Roman Lysecky
Article No.: 105
DOI: 10.1145/3047498

Data-adaptable embedded systems operate on a variety of data streams, which requires a large degree of configurability and adaptability to support runtime changes in data stream inputs. Data-adaptable reconfigurable embedded systems, when...

Real-Time Simulation Support for Runtime Verification of Cyber-Physical Systems
Xi Zheng, Christine Julien, Hongxu Chen, Rodion Podorozhny, Franck Cassez
Article No.: 106
DOI: 10.1145/3063382

In Cyber-Physical Systems (CPS), cyber and physical components must work seamlessly in tandem. Runtime verification of CPS is essential yet very difficult, due to deployment environments that are expensive, dangerous, or simply impossible to use...

Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems
Kaisheng Ma, Xueqing Li, Huichu Liu, Xiao Sheng, Yiqun Wang, Karthik Swaminathan, Yongpan Liu, Yuan Xie, John Sampson, Vijaykrishnan Narayanan
Article No.: 107
DOI: 10.1145/3077575

Self-powered systems running on scavenged energy will be a key enabler for pervasive computing across the Internet of Things. The variability of input power in energy-harvesting systems limits the effectiveness of static optimizations aimed at...

Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform
Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay
Article No.: 108
DOI: 10.1145/3055512

In Network-on-Chip (NoC)-based multicore systems, task allocation and scheduling are known to be important problems, as they affect the performance of applications in terms of energy consumption and timing. Advancement of deep submicron technology...

Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA
Prashant Ahir, Mehran Mozaffari-Kermani, Reza Azarderakhsh
Article No.: 109
DOI: 10.1145/3055514

The widespread use of sensitive and constrained applications necessitates lightweight (low-power and low-area) algorithms developed for constrained nano-devices. However, nearly all of such algorithms are optimized for platform-based performance...

Exploiting Multiple Write Modes of Nonvolatile Main Memory in Embedded Systems
Chen Pan, Mimi Xie, Chengmo Yang, Yiran Chen, Jingtong Hu
Article No.: 110
DOI: 10.1145/3063130

Existing Nonvolatile Memories (NVMs) have many attractive features to be the main memory of embedded systems. These features include low power, high density, and better scalability. Recently, Multilevel Cell (MLC) NVM has gained more and more...

WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory
Yooseong Kim, David Broman, Aviral Shrivastava
Article No.: 112
DOI: 10.1145/3063383

Scratchpad memory (SPM) is a promising on-chip memory choice in real-time and cyber-physical systems where timing is of the utmost importance. SPM has time-predictable characteristics since its data movement between the SPM and the main memory is...

Petri Net Models and Collaborativeness for Parallel Processes with Resource Sharing and Message Passing
Guanjun Liu, Mengchu Zhou, Changjun Jiang
Article No.: 113
DOI: 10.1145/2810001

Petri nets are widely used to model and analyse concurrent systems. There exist two distinct classes of Petri nets that focus on different features of concurrent systems. The first one features multiple parallel processes sharing a group of common...

Efficient Automated Code Partitioning for Microcontrollers with Switchable Memory Banks
Michal Ciszewski, Konrad Iwanicki
Article No.: 114
DOI: 10.1145/3055511

Switching active memory banks at runtime allows a processor with a narrow address bus to access memory that exceeds ranges normally addressable via the bus. Switching code memory banks is regaining interest in microcontrollers for the Internet of...

Efficient Kernel Management on GPUs
Yun Liang, Xiuhong Li
Article No.: 115
DOI: 10.1145/3070710

Graphics Processing Units (GPUs) have been widely adopted as accelerators for compute-intensive applications due to its tremendous computational power and high memory bandwidth. As the complexity of applications continues to grow, each new...

Exploiting Stable Data Dependency in Stream Processing Acceleration on FPGAs
Yuliang Sun, Lanjun Wang, Chen Wang, Yu Wang
Article No.: 116
DOI: 10.1145/3092950

With the unique feature of fine-grained parallelism, field-programmable gate arrays (FPGAs) show great potential for streaming algorithm acceleration. However, the lack of a design framework, restrictions on FPGAs, and ineffective tools...

High-Performance Ideal Lattice-Based Cryptography on 8-Bit AVR Microcontrollers
Zhe Liu, Thomas Pöppelmann, Tobias Oder, Hwajeong Seo, Sujoy Sinha Roy, Tim Güneysu, Johann Großschädl, Howon Kim, Ingrid Verbauwhede
Article No.: 117
DOI: 10.1145/3092951

Over recent years lattice-based cryptography has received much attention due to versatile average-case problems like Ring-LWE or Ring-SIS that appear to be intractable by quantum computers. In this work, we evaluate and compare implementations of...