ACM DL

Embedded Computing Systems (TECS)

Menu

Search Issue
enter search term and/or author name

Archive


ACM Transactions on Embedded Computing Systems (TECS), Volume 2 Issue 4, November 2003

Tiny instruction caches for low power embedded systems
Ann Gordon-Ross, Susan Cotterell, Frank Vahid
Pages: 449-481
DOI: 10.1145/950162.950163
Instruction caches have traditionally been used to improve software performance. Recently, several tiny instruction cache designs, including filter caches and dynamic loop caches, have been proposed to instead reduce software power. We propose...

Compressing MIPS code by multiple operand dependencies
Kelvin Lin, Chung-Ping Chung, Jean Jyh-Jiun Shann
Pages: 482-508
DOI: 10.1145/950162.950164
Intuitively, destination registers of some instructions have great possibilities to be used as the source registers of the immediately subsequent instructions. Such destination register/source register pairs have been exploited previously to improve...

Speculating to reduce unnecessary power consumption
Enric Musoll
Pages: 509-536
DOI: 10.1145/950162.950165
The power consumption of current processors keeps increasing in spite of aggressive circuit design techniques and process shrinks. One of the reasons for this increase is the complexity of the microarchitecture required to achieve the performance...

Maximizing rewards for real-time applications with energy constraints
Cosmin Rusu, Rami Melhem, Daniel Mossé
Pages: 537-559
DOI: 10.1145/950162.950166
New technologies have brought about a proliferation of embedded systems, which vary from control systems to sensor networks to personal digital assistants. Many of the portable embedded devices run several applications, which typically have three...

Automatic compilation to a coarse-grained reconfigurable system-opn-chip
Girish Venkataramani, Walid Najjar, Fadi Kurdahi, Nader Bagherzadeh, Wim Bohm, Jeff Hammes
Pages: 560-589
DOI: 10.1145/950162.950167
The rapid growth of device densities on silicon has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, one of the obstacles to the wider acceptance of this technology is its programmability. The...

Code size reduction technique and implementation for software-pipelined DSP applications
Qingfeng Zhuge, Bin Xiao, Edwin H.-M. Sha
Pages: 590-613
DOI: 10.1145/950162.950168
Software pipelining technique is extensively used to exploit instruction-level parallelism of loops, but also significantly expands the code size. For embedded systems with very limited on-chip memory resources, code size becomes one of the most...