Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS), Volume 3 Issue 1, February 2004

Guest editorial: Special issue on networked embedded systems
Rajesh Gupta
Pages: 1-2
DOI: 10.1145/972627.972628

Energy efficient wireless packet scheduling and fair queuing
Vijay Raghunathan, Saurabh Ganeriwal, Mani Srivastava, Curt Schurgers
Pages: 3-23
DOI: 10.1145/972627.972629
As embedded systems are being networked, often wirelessly, an increasingly larger share of their total energy budget is due to the communication. This necessitates the development of power management techniques that address communication subsystems,...

Self-configuring localization systems: Design and Experimental Evaluation
Nirupama Bulusu, John Heidemann, Deborah Estrin, Tommy Tran
Pages: 24-60
DOI: 10.1145/972627.972630
Embedded networked sensors promise to revolutionize the way we interact with our physical environment and require scalable, ad hoc deployable and energy-efficient node localization/positioning.This paper describes the motivation, design,...

Sensor deployment and target localization in distributed sensor networks
Yi Zou, Krishnendu Chakrabarty
Pages: 61-91
DOI: 10.1145/972627.972631
The effectiveness of cluster-based distributed sensor networks depends to a large extent on the coverage provided by the sensor deployment. We propose a virtual force algorithm (VFA) as a sensor deployment strategy to enhance the coverage after an...

Design of secure cryptography against the threat of power-attacks in DSP-embedded processors
Catherine H. Gebotys
Pages: 92-113
DOI: 10.1145/972627.972632
Embedded wireless devices require secure high-performance cryptography in addition to low-cost and low-energy dissipation. This paper presents for the first time a design methodology for security on a VLIW complex DSP-embedded processor core....

Modeling and validation of pipeline specifications
Prabhat Mishra, Nikil Dutt
Pages: 114-139
DOI: 10.1145/972627.972633
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip design process. Many existing approaches employ a bottom-up approach to pipeline validation, where the functionality of an existing pipelined processor is, in...

Processor-memory coexploration using an architecture description language
Prabhat Mishra, Mahesh Mamidipaka, Nikil Dutt
Pages: 140-162
DOI: 10.1145/972627.972634
Memory represents a major bottleneck in modern embedded systems in terms of cost, power, and performance. Traditionally, memory organizations for programmable embedded systems assume a fixed cache hierarchy. With the widening processor--memory gap,...

Compiling with code-size constraints
Mayur Naik, Jens Palsberg
Pages: 163-181
DOI: 10.1145/972627.972635
Most compilers ignore the problems of limited code space in embedded systems. Designers of embedded software often have no better alternative than to manually reduce the size of the source code or even the compiled code. Besides being tedious and...

Iterative schedule optimization for voltage scalable distributed embedded systems
Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
Pages: 182-217
DOI: 10.1145/972627.972636
We present an iterative schedule optimization for multirate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs). To achieve a high degree of energy reduction, we...

Energy savings and speedups from partitioning critical software loops to hardware in embedded systems
Greg Stitt, Frank Vahid, Shawn Nematbakhsh
Pages: 218-232
DOI: 10.1145/972627.972637
We present results of extensive hardware/software partitioning experiments on numerous benchmarks. We describe our loop-oriented partitioning methodology for moving critical code from hardware to software. Our benchmarks included programs from...