ACM DL

ACM Transactions on

Embedded Computing Systems (TECS)

Menu
Latest Articles

BlueIO: A Scalable Real-Time Hardware I/O Virtualization System for Many-core Embedded Systems

In safety-critical systems, time predictability is vital. This extends to I/O operations that require predictability, timing-accuracy, parallel access, scalability, and isolation. Currently, existing approaches cannot achieve all these requirements at the same time. In this article, we propose a framework of hardware framework for real-time I/O... (more)

Design-Level and Code-Level Security Analysis of IoT Devices

The Internet of Things (IoT) is playing an important role in different aspects of our lives. Smart grids, smart cars, and medical devices all... (more)

Lightweight Implementations of NIST P-256 and SM2 ECC on 8-bit Resource-Constraint Embedded Device

Elliptic Curve Cryptography (ECC) now is one of the most important approach to instantiate... (more)

Compact and Flexible FPGA Implementation of Ed25519 and X25519

This article describes a field-programmable gate array (FPGA) cryptographic architecture, which combines the elliptic curve--based Ed25519 digital... (more)

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have... (more)

Ensuring Secure Application Execution and Platform-Specific Execution in Embedded Devices

The Internet of Things (IoT) is expanding at a large rate, with devices found in commercial and domestic settings from industrial sensors to home... (more)

A Lightweight and Secure Data Collection Serverless Protocol Demonstrated in an Active RFIDs Scenario

In the growing Internet of Things context, thousands of computing devices with various... (more)

A Lightweight Cryptographic Protocol with Certificateless Signature for the Internet of Things

The universality of smart-devices has brought rapid development and the significant advancement of... (more)

NEWS

About TECS 

The design of embedded computing systems, both the software and hardware, increasingly relies on sophisticated algorithms, analytical models, and methodologies. ACM Transactions on Embedded Computing Systems (TECS) aims to present the leading work relating to the analysis, design, behavior, and experience with embedded computing systems. 

READ MORE

TECS Editor-in-Chief featured in "People of ACM"

Sandeep K. Shukla was recently reappointed as Editor-in-Chief of ACM Transactions on Embedded Computing Systems (TECS), and he was featured in the periodic series "People of ACM".  Full article.

Forthcoming Articles
NQA: A New Adaptive Anti-collision Algorithm for RFID Systems

Radio frequency identification (RFID) systems, as one of the key components in Internet of Things (IoT), have attracted much attention in industry and academia. In practice, the performance of an RFID system highly depends on the anti-collision al- gorithm designed for the system. Although numerous research works have been done to design and improve anti-collision algorithms such as the Q-algorithm (QA) which successfully utilized in EPCglobal Class-1 Generation-2 protocol, the per- formance of these anti-collision algorithms is still low. This paper aims to improve the performance of the QA algorithm by reducing its redundant pre-processing time.

Reflections on the History of Cyber-Physical vs. Embedded Systems

Self-Adaptive QoS Management at Communication and Computation Levels for Many-Core SoCs

This work presents a self-adaptive QoS management for many-cores. The first contribution is a self-adaptive QoS management addressing both communication and computation levels, considering proactive and reactive decisions. The second contribution is an online profile learning, enabling the QoS management to be aware of the applications' profile, allowing it to take the proactive decisions based on a prediction analysis. Results show that the proactive decision learns about the applications' profile, and can prevent future interference. The synergy of reactive and proactive decisions sustain the QoS, reducing the deadline miss rate by 99.5% when faced with severe communication and computation disturbances.

A Failure-Aware Dual-Channel Solar Power System for Nonvolatile Sensor Nodes

A design-time and run-time co-optimization framework for dual-channel energy harvesting architecture is proposed in this paper. At design stage, we develop a task failure rate estimation framework to balance design costs and failure rate. At run-time, we propose a failure-aware quality-of-service (QoS) tuning algorithm to further enhance energy efficiency with nearly zero failure rate penalty. Through the experiments on both a simulation platform and a prototype board, this study demonstrates a 27% reduction on failure rate under identical design costs compared with conventional architectures. And the proposed online QoS tuning algorithm brings up to 30% improvement in energy efficiency.

Thermal-Aware Real-Time Scheduling using Timed Continuous Petri Nets

This work presents a thermal aware, real-time, fluid-scheduler for a multiprocessor system with three novel aspects. The first one is a modelling methodology based on Timed Continuous Petri nets ($TCPN$) leading to a complete state variable model, including job arrivals, $CPU$ usage, power and thermal aspects. It provides an accurate model, avoiding the calibration stage of RC thermal equivalent models. Based on this model, the second one is the determination of the existence of a feasible hard real-time thermal aware schedule. The third novelty is a two-step controller implementing a global scheduler capable of managing context switching and migrations.

A survey of asynchronous programming using coroutines in the Internet of Things and embedded systems

Many Internet of Things and embedded projects are event-driven, and therefore require asynchronous and concurrent programming. Current proposals for C++2020 suggest that coroutines will have native language support. It is timely to survey the current use of coroutines in embedded systems development. This paper investigates existing research which uses or describes coroutines on resource-constrained platforms. The existing research is analysed with regard to: software platform, hardware platform and capacity; use cases and intended benefits; and the application programming interface design used for coroutines. A systematic mapping study was performed, to select studies published between 2007 and 2018 which contained original research into the application of coroutines on resource-constrained platforms. An initial set of 566 candidate papers, collated from on-line databases, were reduced to only 35 after filters were applied, revealing the following taxonomy. The C & C++ programming languages were used by 22 studies out of 35. As regards hardware, 16 studies used 8- or 16-bit processors while 13 used 32-bit processors. The four most common use cases were concurrency (17 papers), network communication (15), sensor readings (9) and data flow (7). The leading intended benefits were code style and simplicity (12 papers), scheduling (9) and efficiency (8). A wide variety of techniques have been used to implement coroutines, including native macros, additional tool-chain steps, new language features and non-portable assembly language. We conclude that there is widespread demand for coroutines on resource-constrained devices. Our findings suggest that there is significant demand for a formalised, stable, well-supported implementation of coroutines in C++, designed with consideration of the special needs of resource-constrained devices, and further that such an implementation would bring benefits specific to such devices.

Optimal Power Management for Solar Energy Harvesting Systems

We present a formal study on optimizing the energy consumption of energy harvesting embedded systems. We also propose the Stochastic Power Management (SPM) scheme, that builds statistical models of harvest energy based on historical data. SPM maximizes the minimum energy consumption over all time intervals, while giving strict probabilistic guarantees on not encountering battery depletion. For situations where historical data is not available, we propose the use of a Finite Horizon Control (FHC) scheme. We quantitatively establish that the proposed solutions are highly effective at providing a guaranteed minimum service level, and significantly out-perform existing solutions.

Introduction to the Special Issue on Cryptographic Engineering for Internet of Things: Security Foundations, Lightweight Solutions, and Attacks

Catching escaper: A Detection Method for Advanced Persistent Escaper in Industry Internet of Things

With Industry 4.0 or Internet of Things (IoT) era coming, security problem plays a key role in Industry Internet of Things (IIoT), from escape or DDoS attackers in virtualization layer to vulnerability exploiter in device layer. It will be a great threat while a cross-vm escape in virtualization is successfully performed combined with a cross-layer penetration in devices, which is called as Advanced Persistent Escaper (APE) in our definition. Therefore, how to detect APE across multi-layers in IIoT is an open issue. To our best knowledge, no effective method is established, especially for vulnerability exploitation in virtualization and backdoor leverage in devices. To deal with these problems, we propose EscaperCOP, a detection method for cross-VM Escapers in virtualization layer and cross-layer penetrators in device layer. In detail, a new detection method to catch Guest-to-Host escaper is proposed for virtualization layer, furthermore our detection should find illegal host-to-guest command and guest-to-device control based on semi-supervised deep learning. To verify our proposal, experimental tests are accomplished in a large number of APEs in IIoT framework, test results have demonstrated that we can detect designed APEs successfully, and related efficiency is evaluated as an acceptable level.

Partitioning and Selection of Data Consistency Mechanisms for Multicore Real-Time Systems

Multicore platforms are becoming increasingly popular in real-time systems. One of the major challenges in designing multicore real-time systems is ensuring consistent and timely access to shared resources. Lock-based protection mechanisms such as MPCP and MSRP have been proposed to guarantee mutually exclusive access in multicore systems at the expense of blocking. In this paper, we consider partitioning and scheduling in multicore real-time systems with resource sharing. We first propose a resource-aware task partitioning algorithm for systems with lock-based protection. Wait-free methods, which ensure consistent access to shared memory resources with negligible blocking at the expense of additional memory space, are a suitable alternative when the shared resource is a communication buffer. We propose several approaches to solve the joint problem of task partitioning and the selection of data consistency mechanism (lock-based or wait-free). The problem is first formulated as an Integer Linear Programming (ILP). For large systems where an ILP solution is not scalable, we propose two heuristic algorithms. Experimental results compare the effectiveness of the proposed approaches in finding schedulable systems with low memory cost and show how the use of wait-free methods can significantly improve schedulability.

Optimization and Implementation of Wavelet Based Algorithms for Detecting HVS in Neuron Signals

A MCU based Sim-DWT algorithm that can detect high-voltage spindles (HVSs) in local eld potential signals. The requirement of only sixteen 8-bit sample points as the window length for calculation and no need for a multiplier render the Sim-DWT easy to implement in an MCU with limited hardware resources. The Sim-DWT is applied in an 8-bit MCU and was tested for detecting LFP signals in vivo. The design methods and the accuracy of three typical types of mother wavelet functions (Haar, DB4, Morlet) in the Sim-DWT were also tested and compared with those of a PC-based system.

Cooperative Cache Transfer based On-demand Network Coded Broadcast in Vehicular Networks

Real-time traffic updates, safety and comfort driving, infotainment etc. are some envisioned applications in vehicular networks. In the traditional network coding assisted broadcast, the explicit cache upload from vehicles to RSU wastes upload bandwidth. In multi-RSU vehicular networks, we propose a Cooperative Cache Transfer based on-demand network Coded Broadcast called CCTCB. In the proposed CCTCB approach, the RSU server learns the vehicles' cache intrinsically. We derive a probabilistic model to analyze the coding opportunity in the proposed cooperative cache transfer mechanism incorporating vehicle mobility. The comprehensive simulation results validate the superiority of the proposed approach.

A Contention Detectable Mechanism for Receiver-Initiated MAC in Wireless Sensor Networks

In this paper, we present Contention Detectable MAC (CD-MAC), an energy efficient and robust duty-cycled MAC for general wireless sensor network applications. By exploring the temporal diversity of the acknowledgements, a receiver recognizes the potential senders and subsequently polls individual senders one by one. We further design efficient algorithm to avoid the possible acknowledgement collisio

Enabling On-the-Fly Hardware Tracing of Data Reads in Multicores

Software debugging is one of the most challenging aspects of embedded system development due to growing hardware and software complexity, limited visibility of system components, and tightening time-to-market. To find software bugs faster, developers often rely on on-chip trace modules with large buffers to capture program execution traces with minimum interference with program execution. However, high volumes of trace data and high cost of trace modules limit the visibility into the system operation to short program segments. This paper introduces a new hardware/software technique for capturing and filtering read data value traces in multicores that enables a complete reconstruction of parallel program execution. The proposed technique exploits tracking of data reads in data caches and cache coherence protocol states to minimize the number of trace messages streamed out of the target platform to the software debugger. The effectiveness of the proposed technique is determined by analyzing the required trace port bandwidth and trace buffer sizes as a function of the data cache size and the number of processor cores. The results show that the proposed technique significantly reduces the required trace port bandwidth, from 12.2 to 73.9 times, when compared to the Nexus-like read data value tracing, thus enabling continuous on-the-fly data tracing at modest hardware cost.

All ACM Journals | See Full Journal Index

Search TECS
enter search term and/or author name