Reflections on the History of Cyber-Physical vs. Embedded Systems
A design-time and run-time co-optimization framework for dual-channel energy harvesting architecture is proposed in this paper. At design stage, we develop a task failure rate estimation framework to balance design costs and failure rate. At run-time, we propose a failure-aware quality-of-service (QoS) tuning algorithm to further enhance energy efficiency with nearly zero failure rate penalty. Through the experiments on both a simulation platform and a prototype board, this study demonstrates a 27% reduction on failure rate under identical design costs compared with conventional architectures. And the proposed online QoS tuning algorithm brings up to 30% improvement in energy efficiency.
This work presents a thermal aware, real-time, fluid-scheduler for a multiprocessor system with three novel aspects. The first one is a modelling methodology based on Timed Continuous Petri nets ($TCPN$) leading to a complete state variable model, including job arrivals, $CPU$ usage, power and thermal aspects. It provides an accurate model, avoiding the calibration stage of RC thermal equivalent models. Based on this model, the second one is the determination of the existence of a feasible hard real-time thermal aware schedule. The third novelty is a two-step controller implementing a global scheduler capable of managing context switching and migrations.
The Internet of Things (IoT) is playing an important role in different aspects of our lives. Smart grids, smart cars, and medical devices all incorporate IoT devices as key components. The ubiquity and criticality of these devices make them an attractive target for attackers. Therefore, we need techniques to analyze their security, so that we can address their potential vulnerabilities. Security analysis techniques may operate at the design-level, to avoid state-space explosion, or at the code-level for ensuring accuracy. In this paper we introduce one techniques for each category, and compare their effectiveness on a real IoT testbed.
Many Internet of Things and embedded projects are event-driven, and therefore require asynchronous and concurrent programming. Current proposals for C++2020 suggest that coroutines will have native language support. It is timely to survey the current use of coroutines in embedded systems development. This paper investigates existing research which uses or describes coroutines on resource-constrained platforms. The existing research is analysed with regard to: software platform, hardware platform and capacity; use cases and intended benefits; and the application programming interface design used for coroutines. A systematic mapping study was performed, to select studies published between 2007 and 2018 which contained original research into the application of coroutines on resource-constrained platforms. An initial set of 566 candidate papers, collated from on-line databases, were reduced to only 35 after filters were applied, revealing the following taxonomy. The C & C++ programming languages were used by 22 studies out of 35. As regards hardware, 16 studies used 8- or 16-bit processors while 13 used 32-bit processors. The four most common use cases were concurrency (17 papers), network communication (15), sensor readings (9) and data flow (7). The leading intended benefits were code style and simplicity (12 papers), scheduling (9) and efficiency (8). A wide variety of techniques have been used to implement coroutines, including native macros, additional tool-chain steps, new language features and non-portable assembly language. We conclude that there is widespread demand for coroutines on resource-constrained devices. Our findings suggest that there is significant demand for a formalised, stable, well-supported implementation of coroutines in C++, designed with consideration of the special needs of resource-constrained devices, and further that such an implementation would bring benefits specific to such devices.
We present a formal study on optimizing the energy consumption of energy harvesting embedded systems. We also propose the Stochastic Power Management (SPM) scheme, that builds statistical models of harvest energy based on historical data. SPM maximizes the minimum energy consumption over all time intervals, while giving strict probabilistic guarantees on not encountering battery depletion. For situations where historical data is not available, we propose the use of a Finite Horizon Control (FHC) scheme. We quantitatively establish that the proposed solutions are highly effective at providing a guaranteed minimum service level, and significantly out-perform existing solutions.
Introduction to the Special Issue on Cryptographic Engineering for Internet of Things: Security Foundations, Lightweight Solutions, and Attacks
With Industry 4.0 or Internet of Things (IoT) era coming, security problem plays a key role in Industry Internet of Things (IIoT), from escape or DDoS attackers in virtualization layer to vulnerability exploiter in device layer. It will be a great threat while a cross-vm escape in virtualization is successfully performed combined with a cross-layer penetration in devices, which is called as Advanced Persistent Escaper (APE) in our definition. Therefore, how to detect APE across multi-layers in IIoT is an open issue. To our best knowledge, no effective method is established, especially for vulnerability exploitation in virtualization and backdoor leverage in devices. To deal with these problems, we propose EscaperCOP, a detection method for cross-VM Escapers in virtualization layer and cross-layer penetrators in device layer. In detail, a new detection method to catch Guest-to-Host escaper is proposed for virtualization layer, furthermore our detection should find illegal host-to-guest command and guest-to-device control based on semi-supervised deep learning. To verify our proposal, experimental tests are accomplished in a large number of APEs in IIoT framework, test results have demonstrated that we can detect designed APEs successfully, and related efficiency is evaluated as an acceptable level.
Multicore platforms are becoming increasingly popular in real-time systems. One of the major challenges in designing multicore real-time systems is ensuring consistent and timely access to shared resources. Lock-based protection mechanisms such as MPCP and MSRP have been proposed to guarantee mutually exclusive access in multicore systems at the expense of blocking. In this paper, we consider partitioning and scheduling in multicore real-time systems with resource sharing. We first propose a resource-aware task partitioning algorithm for systems with lock-based protection. Wait-free methods, which ensure consistent access to shared memory resources with negligible blocking at the expense of additional memory space, are a suitable alternative when the shared resource is a communication buffer. We propose several approaches to solve the joint problem of task partitioning and the selection of data consistency mechanism (lock-based or wait-free). The problem is first formulated as an Integer Linear Programming (ILP). For large systems where an ILP solution is not scalable, we propose two heuristic algorithms. Experimental results compare the effectiveness of the proposed approaches in finding schedulable systems with low memory cost and show how the use of wait-free methods can significantly improve schedulability.
In this paper, we present Contention Detectable MAC (CD-MAC), an energy efficient and robust duty-cycled MAC for general wireless sensor network applications. By exploring the temporal diversity of the acknowledgements, a receiver recognizes the potential senders and subsequently polls individual senders one by one. We further design efficient algorithm to avoid the possible acknowledgement collisio
Software debugging is one of the most challenging aspects of embedded system development due to growing hardware and software complexity, limited visibility of system components, and tightening time-to-market. To find software bugs faster, developers often rely on on-chip trace modules with large buffers to capture program execution traces with minimum interference with program execution. However, high volumes of trace data and high cost of trace modules limit the visibility into the system operation to short program segments. This paper introduces a new hardware/software technique for capturing and filtering read data value traces in multicores that enables a complete reconstruction of parallel program execution. The proposed technique exploits tracking of data reads in data caches and cache coherence protocol states to minimize the number of trace messages streamed out of the target platform to the software debugger. The effectiveness of the proposed technique is determined by analyzing the required trace port bandwidth and trace buffer sizes as a function of the data cache size and the number of processor cores. The results show that the proposed technique significantly reduces the required trace port bandwidth, from 12.2 to 73.9 times, when compared to the Nexus-like read data value tracing, thus enabling continuous on-the-fly data tracing at modest hardware cost.