ACM Transactions on

Embedded Computing Systems (TECS)

Latest Articles

Providing Accountability in Heterogeneous Systems-on-Chip

When modern systems-on-chip (SoCs), containing designs from different organizations, miscompute or underperform in the field, discerning the... (more)

Energy-Efficient Real-Time Scheduling of DAG Tasks

This work studies energy-aware real-time scheduling of a set of sporadic Directed Acyclic Graph (DAG) tasks with implicit deadlines. While meeting all... (more)

Packet Aggregation Real-Time Scheduling for Large-Scale WIA-PA Industrial Wireless Sensor Networks

The IEC standard WIA-PA is a communication protocol for industrial wireless sensor networks. Its... (more)


About TECS 

The design of embedded computing systems, both the software and hardware, increasingly relies on sophisticated algorithms, analytical models, and methodologies. ACM Transactions on Embedded Computing Systems (TECS) aims to present the leading work relating to the analysis, design, behavior, and experience with embedded computing systems. 


TECS Editor-in-Chief featured in "People of ACM"

Sandeep K. Shukla was recently reappointed as Editor-in-Chief of ACM Transactions on Embedded Computing Systems (TECS), and he was featured in the periodic series "People of ACM".  Full article.

Forthcoming Articles
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs

We present a hybrid application methodology comprising a design space exploration with a formal performance analysis for individual applications. This results in several resource reservation configurations with verified real-time guarantees. The Pareto-optimal configurations are handed over to run-time management which searches for a suitable mapping. We achieve real-time guarantees through the concept of composability either by spatial or a novel temporal isolation for tasks and by exploiting composable NoCs. The experiments reveal that the success rate in finding feasible application mappings is increased by temporal isolation by up to 30% and energy consumption is reduced compared to spatial isolation.

Schedule Adaptation for Ensuring Reliability in RT-WiFi-Based Networked Embedded Systems

In this paper, we explicitly consider interference from both Wi-Fi and non-Wi-Fi based interference sources, and propose two sets of effective solutions for reliable data transmissions in RT-WiFi based networked embedded systems. To improve reliability against general non-Wi-Fi based interference, based on rate adaptation and retransmission techniques, we present an optimal real-time rate adaption algorithm together with a communication link scheduler that has low network management overhead. For Wi-Fi based interference, we present mechanisms that utilize virtual carrier sensing to provide reliable data transmission while co-existing with regular Wi-Fi networks.

Compositional Dataflow Circuits

We present a technique for implementing dataflow networks as compositional hardware circuits. We first define an abstract dataflow model with unbounded buffers that supports data-dependent blocks (mux, demux, and nondeterministic merge); we then show how to faithfully implement such networks with bounded buffers and handshaking. Handshaking admits compositionality: our circuits can be connected with or without buffers and still compute the same function without introducing spurious combinational cycles. As such, inserting or removing buffers affects the performance but not the functionality of our networks; which we demonstrate through experiments that show how design space can be explored.

Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis

We explore techniques to reverse-engineer DRAM embedded memory controllers (MCs) including page policies, address mapping and command arbitration. There are several benefits to knowing this information: they allow tightening worst-case bounds of embedded systems, and platform-aware optimizations at the operating system, source-code, and compiler levels. We develop a latency-based analysis, which we use to devise algorithms and C programs to extract MC properties. We show the effectiveness of the proposed approach by reverse-engineering the MC details in the XUPV5-LX110T Xilinx platform. Furthermore, in order to cover a breadth of policies, we use a simulation framework and document our finding.

OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures

Heterogeneous architectures have been proposed for meeting the ever increasing performance and power requirements of embedded systems. However, the existence of numerous design parameters may result in extra design effort. OpenCL-based frameworks have been recently utilized for FPGA programming, in order to enable the portability of a source code to multiple architectures. However, such OpenCL frameworks focus on RTL design, thus not enabling rapid prototyping. Virtual Prototyping aims to overcome this problem by enabling the system modeling in higher abstraction levels. This article combines the benefits of OpenCL and Virtual Prototyping by proposing an OpenCL-based prototyping framework for data-parallel many-accelerators.

Lightweight Implementations of NIST P-256 and SM2 ECC on 8-bit Resource-Constraint Embedded Device

Elliptic Curve Cryptography (ECC) now is one of the most important approach to instantiate asymmetric encryption and signature schemes, which has been extensively exploited to protect the security of cyber-physical systems. With the advent of the Internet of Things (IoT), a great deal of constrained devices may require software implementations of ECC operations. Under this circumstances, the SM2, a set of public key cryptographic algorithms based on elliptic curves published by Chinese Commercial Cryptography Administration Office, was standardized at ISO in 2017 to enhance the cyber-security. However, few research works on implementations of SM2 for constrained devices have been conducted. In this work, we fill this gap and propose our efficient, secure and compact implementation of scalar multiplication on a 256-bit elliptic curve recommended by the SM2, as well as a comparison implementation of scalar multiplication on the same bit-length elliptic curve recommended by NIST. We re-designed some existent techniques to fit the low-end IoT platform, namely 8-bit AVR processors, and our ECC implementations evaluated on the desired platform show that the SM2 algorithms have competitive efficiency and security with NIST, which would work well to secure the IoT world.

The Mechanized Marriage of Effects and Monads with Applications to High Assurance Hardware

Constructing high assurance, secure hardware remains a challenge, because to do so relies on both a verifiable means of hardware description and implementation. Production hardware description languages (HDL) lack the formal underpinnings required by formal methods in security. Still, there is no such thing as high assurance systems without high assurance hardware. We present a core calculus of secure hardware description with its formal semantics, security type system and mechanization in Coq. This calculus is the core of the functional HDL, ReWire. This work supports a full-fledged formal methodology for producing high assurance hardware.

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for Internet based on classical cryptography cannot be applied to IoT nodes due to the resource-constrained platform. A physical unclonable function (PUF) can be used to generate a key online or uniquely identify an integrated circuits (ICs) by extracting its internal random differences using the so-called challenge-response pairs (CRPs). The PUF is a new type of hardware-based security primitive; it is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This paper first presents a new classification of RPUFs into circuit based RPUF (C-RPUF) and algorithm based RPUF (A-RPUF); two XOR-based RPUF circuits (namely the XOR-based reconfigurable bistable ring PUF (XRBR PUF) and the XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented using Xilinx Spartan-6 FPGAs. The implementation results are compared with previous PUF designs showing a good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response; this confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability.

Stochastic Assume-Guarantee Contracts for Cyber-Physical System Design

We develop an assume-guarantee contract framework for cyber-physical system design under probabilistic requirements. Given a stochastic linear system and a set of requirements captured by bounded Stochastic Signal Temporal Logic (StSTL) contracts, we propose algorithms to check contract compatibility, consistency, and refinement, and generate a control trajectory that satisfies a contract. We leverage encodings of the verification and control synthesis tasks into mixed integer optimization problems, and conservative approximations of probabilistic constraints that produce sound and tractable problem formulations. We illustrate the effectiveness of our approach on a few examples, including the design of controllers for aircraft power distribution networks.

A Lightweight & Secure Data Collection Serverless Protocol Demonstrated in an Active RFIDs scenario

In the growing Internet of Things context, thousands of computing devices with various functionalities are producing data (from environmental sensors or other sources). However, they are also collecting, storing, processing and transmitting data to eventually communicate them securely to third parties (e.g. owners of devices or cloud data storage). The deployed devices are often battery-powered mobile or static nodes equipped with sensors and/or actuators and they communicate using wireless technologies. Examples include unmanned aerial vehicles, wireless sensor nodes, smart beacons, and wearable health objects. Such resource-constrained devices include Active RFID (Radio Frequency IDentification) nodes and these are used to illustrate our proposal. In most scenarios, these nodes are unattended in an adverse environment, so data confidentiality must be ensured from the sensing phase through to delivery to authorized entities: in other words, data must be securely stored and transmitted to prevent attack by active adversaries even if the nodes are captured. However, due to the scarce resources available to nodes in terms of energy, storage and/or computation, the proposed security solution has to be lightweight. In this paper, we propose a serverless protocol to enable MDCs (Mobile Data Collectors), such as drones, to securely collect data from mobile and static Active RFID nodes and then deliver them later to an authorized third party. The whole solution ensures data confidentiality at each step (from the sensing phase, before data collection by the MDC, once data have been collected by MDC, and during final delivery) while fulfilling the lightweight requirements for the resource-limited entities involved. To assess the suitability of the protocol against the performance requirements, it was implemented on the most resource-constrained devices to get the worst possible results. In addition, to prove the protocol fulfills the security requirements, it was analyzed with regard to security games and also formally verified using the AVISPA tool.

A Reconfiguration-Based Fault-Tolerant Anti-Lock Brake-by-Wire System

ABS and Brake-by-Wire Systems (BBW) are safety-critical applications. Such systems are required to demonstrate high degrees of dependability. Fault-tolerance is the primary means to achieve dependability at runtime. Fault-tolerance is usually achieved in ABS and BBW systems through traditional redundancy and voting methods. In such systems hardware units, actuators, sensors, and communication networks are replicated were special voters vote against faulty units. In this paper, we present a reconfiguration-based fault-tolerant approach to achieve high dependability in ABS BBW braking systems. The proposed architecture makes use of other components of less safety-critical systems to maintain high dependability in more safety-critic

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