Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS), Volume 4 Issue 4, November 2005

Rajeev Alur, Insup Lee
Pages: 707-707
DOI: 10.1145/1113830.1113831

Loops in esterel
Olivier Tardieu, Robert de Simone
Pages: 708-750
DOI: 10.1145/1113830.1113832
ESTEREL is a synchronous design language for the specification of reactive systems. Thanks to its compact formal semantics, code generation for ESTEREL is essentially provably correct. In practice, due to the many intricacies of an optimizing...

Eliminating stack overflow by abstract interpretation
John Regehr, Alastair Reid, Kirk Webb
Pages: 751-778
DOI: 10.1145/1113830.1113833
An important correctness criterion for software running on embedded microcontrollers is stack safety: a guarantee that the call stack does not overflow. Our first contribution is a method for statically guaranteeing stack safety of...

Translating discrete-time simulink to lustre
Stavros Tripakis, Christos Sofronis, Paul Caspi, Adrian Curic
Pages: 779-818
DOI: 10.1145/1113830.1113834
We present a method of translating discrete-time Simulink models to Lustre programs. Our method consists of three steps: type inference, clock inference, and hierarchical bottom-up translation. In the process, we explain and formalize the typing and...

Compiler-directed high-level energy estimation and optimization
I. Kadayif, M. Kandemir, G. Chen, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam
Pages: 819-850
DOI: 10.1145/1113830.1113835
The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for power optimization. While many power-oriented hardware optimization techniques have been proposed and incorporated in current...

Analyzing data reuse for cache reconfiguration
J. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin
Pages: 851-876
DOI: 10.1145/1113830.1113836
Classical compiler optimizations assume a fixed cache architecture and modify the program to take best advantage of it. In some cases, this may not be the best strategy because each nest might work best with a different cache configuration and...

Range-free localization and its impact on large scale sensor networks
Tian He, Chengdu Huang, Brian M. Blum, John A. Stankovic, Tarek F. Abdelzaher
Pages: 877-906
DOI: 10.1145/1113830.1113837
With the proliferation of location dependent applications in sensor networks, location awareness becomes an essential capability of sensor nodes. Because coarse accuracy is sufficient for most sensor network applications, solutions in range-free...

Shortest-path algorithms for real-time scheduling of FIFO tasks with minimal energy use
Bruno Gaujal, Nicolas Navet, Cormac Walsh
Pages: 907-933
DOI: 10.1145/1113830.1113838
We present an algorithm for scheduling a set of nonrecurrent tasks (or jobs) with FIFO real-time constraints so as to minimize the total energy consumed when the tasks are performed on a dynamically variable voltage processor. Our algorithm runs in...

Optimizing instruction cache performance of embedded systems
S. Bartolini, C. A. Prete
Pages: 934-965
DOI: 10.1145/1113830.1113839
In the embedded domain, the gap between memory and processor performance and the increase in application complexity need to be supported without wasting precious system resources: die size, power, etc. For these reasons, effective exploitation of...