Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005, Volume 6 Issue 2, May 2007

Guest editorial: Introduction to the special issue on software and compilers for embedded systems
Henk Schepers
Article No.: 9
DOI: 10.1145/1234675.1234676

Selective code transformation for dual instruction set processors
Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
Article No.: 10
DOI: 10.1145/1234675.1234677

Embedded systems are often constrained in terms of both code size and execution time, because of a limited amount of available memory and real-time nature of applications. A dual instruction set processor, which supports a reduced instruction set...

Reducing branch predictor leakage energy by exploiting loops
Wei Zhang, Bramha Allu
Article No.: 11
DOI: 10.1145/1234675.1234678

With the scaling of technology, leakage energy will become the dominant source of energy consumption. Besides cache memories, branch predictors are among the largest on-chip array structures and consume nontrivial leakage energy. This paper...

ASIP architecture exploration for efficient IPSec encryption: A case study
Hanno Scharwaechter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Article No.: 12
DOI: 10.1145/1234675.1234679

Application-Specific Instruction-Set Processors (ASIPs) are becoming increasingly popular in the world of customized, application-driven System-on-Chip (SoC) designs. Efficient ASIP design requires an iterative architecture exploration...

Classifying interprocess communication in process network representation of nested-loop programs
Alexandru Turjan, Bart Kienhuis, Ed Deprettere
Article No.: 13
DOI: 10.1145/1234675.1234680

New embedded signal-processing architectures are emerging that are composed of loosely coupled heterogeneous components like CPUs or DSPs, specialized IP cores, reconfigurable units, or memories. We believe that these architectures should be...

Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls
Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya
Article No.: 14
DOI: 10.1145/1234675.1234681

Synthesis of digital signal-processing (DSP) software from dataflow-based formal models is an effective approach for tackling the complexity of modern DSP applications. In this paper, an efficient method is proposed for applying subroutine call...