Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS), Volume 7 Issue 4, July 2008

Editorial: Embedded systems—new challenges and future directions
Fabiano Hessell, Kenneth Kent, Dionisios Pnevmatikatos
Article No.: 37
DOI: 10.1145/1376804.1376805

A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
Chanik Park, Wonmoon Cheon, Jeonguk Kang, Kangho Roh, Wonhee Cho, Jin-Soo Kim
Article No.: 38
DOI: 10.1145/1376804.1376806

In this article, a novel FTL (flash translation layer) architecture is proposed for NAND flash-based applications such as MP3 players, DSCs (digital still cameras) and SSDs (solid-state drives). Although the basic function of an FTL is to...

Platform-based software design flow for heterogeneous MPSoC
Katalin Popovici, Xavier Guerin, Frederic Rousseau, Pier Stanislao Paolucci, Ahmed Amine Jerraya
Article No.: 39
DOI: 10.1145/1376804.1376807

Current multimedia applications demand complex heterogeneous multiprocessor architectures with specific communication infrastructure in order to achieve the required performances. Programming these architectures usually results in writing separate...

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors
A. Chattopadhyay, H. Ishebabi, X. Chen, Z. Rakosi, K. Karuri, D. Kammler, R. Leupers, G. Ascheid, H. Meyr
Article No.: 40
DOI: 10.1145/1376804.1376808

Modern application-specific instruction-set processors (ASIPs) face the daunting task of delivering high performance for a wide range of applications. For enhancing the performance, architectural features, for example, pipelining, VLIW, are often...

Modeling and analysis of core-centric network processors
Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai, Kuo-Kun Tseng
Article No.: 41
DOI: 10.1145/1376804.1376809

Network processors can be categorized into two types, the coprocessors-centric model in which data-plane is handled by coprocessors, and the core-centric model in which the core processes most of the data-plane packets yet offloading some tasks to...

From the prototype to the final embedded system using the Ocarina AADL tool suite
Jerome Hugues, Bechir Zalila, Laurent Pautet, Fabrice Kordon
Article No.: 42
DOI: 10.1145/1376804.1376810

Building distributed deal-time embedded systems requires a stringent methodology, from early requirement capture to full implementation. However, there is a strong link between the requirements and the final implementation (e.g., scheduling and...

Composing heterogeneous reactive systems
Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli
Article No.: 43
DOI: 10.1145/1376804.1376811

We present a compositional theory of heterogeneous reactive systems. The approach is based on the concept of tags marking the events of the signals of a system. Tags can be used for multiple purposes from indexing evolution in time (time stamping)...

EM analysis of a wireless Java-based PDA
Catherine H. Gebotys, Brian A. White
Article No.: 44
DOI: 10.1145/1376804.1376812

The susceptibility of wireless portable devices to electromagnetic (EM) attacks is largely unknown. If analysis of electromagnetic (EM) waves emanating from the wireless device during a cryptographic computation do leak sufficient information, it...

Implementing fault-tolerance in real-time programs by automatic program transformations
Tolga Ayav, Pascal Fradet, Alain Girault
Article No.: 45
DOI: 10.1145/1376804.1376813

We present a formal approach to implement fault-tolerance in real-time embedded systems. The initial fault-intolerant system consists of a set of independent periodic tasks scheduled onto a set of fail-silent processors connected by a reliable...

MTSS: Multitask stack sharing for embedded systems
Bhuvan Middha, Matthew Simpson, Rajeev Barua
Article No.: 46
DOI: 10.1145/1376804.1376814

Out-of-memory errors are a serious source of unreliability in most embedded systems. Applications run out of main memory because of the frequent difficulty of estimating the memory requirement before deployment, either because it depends on input...