Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS), Volume 8 Issue 3, April 2009

Reducing memory requirements of resource-constrained applications
P. Unnikrishnan, G. Chen, M. Kandemir, M. Karakoy, I. Kolcu
Article No.: 17
DOI: 10.1145/1509288.1509289

Embedded computing platforms are often resource constrained, requiring great design and implementation attention to memory-power-, and heat-related parameters. An important task for a compiler in such platforms is to simplify the process of...

Analytic modeling of network processors for parallel workload mapping
Ning Weng, Tilman Wolf
Article No.: 18
DOI: 10.1145/1509288.1509290

Network processors are heterogeneous system-on-chip multiprocessors that are optimized to perform packet forwarding and processing tasks at Gigabit data rates. To meet the performance demands of increasing link speeds and complex network...

A fast scalable automaton-matching accelerator for embedded content processors
Kuo-Kun Tseng, Yuan-Cheng Lai, Ying-Dar Lin, Tsern-Huei Lee
Article No.: 19
DOI: 10.1145/1509288.1509291

Home and office network gateways often employ a cost-effective embedded network processor to handle their network services. Such network gateways have received strong demand for applications dealing with intrusion detection, keyword blocking,...

Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
Mehrdad Reshadi, Prabhat Mishra, Nikil Dutt
Article No.: 20
DOI: 10.1145/1509288.1509292

Instruction-set simulators are critical tools for the exploration and validation of new processor architectures. Due to the increasing complexity of architectures and time-to-market pressure, performance is the most important feature of an...

Memory allocation for embedded systems with a compile-time-unknown scratch-pad size
Nghi Nguyen, Angel Dominguez, Rajeev Barua
Article No.: 21
DOI: 10.1145/1509288.1509293

This article presents the first memory allocation scheme for embedded systems having a scratch-pad memory whose size is unknown at compile time. A scratch-pad memory (SPM) is a fast compiler-managed SRAM that replaces the hardware-managed cache....

Design and implementation of a MicroBlaze-based warp processor
Roman Lysecky, Frank Vahid
Article No.: 22
DOI: 10.1145/1509288.1509294

While soft processor cores provided by FPGA vendors offer designers with increased flexibility, such processors typically incur penalties in performance and energy consumption compared to hard processor core alternatives. The recently developed...

MEMMU: Memory expansion for MMU-less embedded systems
Lan S. Bai, Lei Yang, Robert P. Dick
Article No.: 23
DOI: 10.1145/1509288.1509295

Random access memory (RAM) is tightly constrained in the least expensive, lowest-power embedded systems such as sensor network nodes and portable consumer electronics. The most widely used sensor network nodes have only 4 to 10KB of RAM and do not...

A novel software framework for embedded multiprocessor smart cameras
Andreas Doblander, Andreas Zoufal, Bernhard Rinner
Article No.: 24
DOI: 10.1145/1509288.1509296

Distributed smart cameras (DSC) are an emerging technology for a broad range of important applications including smart rooms, surveillance, entertainment, tracking, and motion analysis. By having access to many views and through cooperation among...