Embedded Computing Systems (TECS)


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ACM Transactions on Embedded Computing Systems (TECS), Volume 13 Issue 1, August 2013

Sea depth measurement with restricted floating sensors
Mo Li, Zheng Yang, Yunhao Liu
Article No.: 1
DOI: 10.1145/2512448

Sea depth monitoring is a critical task for ensuring safe operation of harbors. Traditional schemes largely rely on labor-intensive work and expensive hardware. This study explores the possibility of deploying networked sensors on the surface of...

A comparison of compositional schedulability analysis techniques for hierarchical real-time systems
Madhukar Anand, Sebastian Fischmeister, Insup Lee
Article No.: 2
DOI: 10.1145/2501626.2501629

Schedulability analysis of hierarchical real-time embedded systems involves defining interfaces that represent the underlying system faithfully and then compositionally analyzing those interfaces. Whereas commonly used abstractions, such as...

Leveraging speculative architectures for runtime program validation
Juan Carlos Martinez Santos, Yunsi Fei
Article No.: 3
DOI: 10.1145/2512456

Program execution can be tampered with by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security....

Thermal-aware memory mapping in 3D designs
Ang-Chih Hsieh, Tingting Hwang
Article No.: 4
DOI: 10.1145/2512457

DRAM is usually used as main memory for program execution. The thermal behavior of a memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a block is related...

A software-only scheme for managing heap data on limited local memory(LLM) multicore processors
Ke Bai, Aviral Shrivastava
Article No.: 5
DOI: 10.1145/2501626.2501632

This article presents a scheme for managing heap data in the local memory present in each core of a limited local memory (LLM) multicore architecture. Although managing heap data semi-automatically with software cache is feasible, it may require...

DLIC: Decoded loop instructions caching for energy-aware embedded processors
Ji Gu, Hui Guo, Tohru Ishihara
Article No.: 6
DOI: 10.1145/2512464

With the explosive proliferation of embedded systems, especially through countless portable devices and wireless equipment used, embedded systems have become indispensable to the modern society and people's life. Those devices are often battery...

L24: Parallelism, performance, energy efficiency, and cost trade-offs in future sensor platforms
Phillip Stanley-Marbell
Article No.: 7
DOI: 10.1145/2512465

Networks of sensors must process large amounts of intermittently-available data in situ. This motivates the investigation of means for achieving high performance when required, but ultra-low-power dissipation when idle. One approach to this...

Software thread integration for instruction-level parallelism
Won So, Alexander G. Dean
Article No.: 8
DOI: 10.1145/2512466

Multimedia applications require a significantly higher level of performance than previous workloads of embedded systems. They have driven digital signal processor (DSP) makers to adopt high-performance architectures like VLIW (Very-Long...

Ultra low-power signal processing in wearable monitoring systems: A tiered screening architecture with optimal bit resolution
Hassan Ghasemzadeh, Roozbeh Jafari
Article No.: 9
DOI: 10.1145/2501626.2501636

Advances in technology have led to the development of wearable sensing, computing, and communication devices that can be woven into the physical environment of our daily lives, enabling a large variety of new applications in several domains,...

A reliability enhancement design under the flash translation layer for MLC-based flash-memory storage systems
Yuan-Hao Chang, Ming-Chang Yang, Tei-Wei Kuo, Ren-Hung Hwang
Article No.: 10
DOI: 10.1145/2512467

Although flash memory has gained very strong momentum in the storage market, the reliability of flash-memory chips has been dropped significantly in the past years. This article presents a reliability enhancement design under the flash management...

Transport-layer-assisted routing for runtime thermal management of 3D NoC systems
Chih-Hao Chao, Kun-Chih Chen, Tsu-Chu Yin, Shu-Yen Lin, An-Yeu (Andy) Wu
Article No.: 11
DOI: 10.1145/2512468

To ensure thermal safety and to avoid performance degradation from temperature regulation in 3D NoC, we propose a new temperature-traffic control framework. The framework contains the vertical throttling-based runtime thermal management (VT-RTM)...

Contextual partitioning for speech recognition
Christopher G. Kent, Joann M. Paul
Article No.: 12
DOI: 10.1145/2501626.2501639

Many multicore computers are single-user devices, creating the potential to partition by situational usage contexts, similar to how the human brain is organized. Contextual partitioning (CP) permits multiple simplified versions of the same task to...

Design and evaluation of random linear network coding Accelerators on FPGAs
Sunwoo Kim, Won Seob Jeong, Won W. Ro, Jean-Luc Gaudiot
Article No.: 13
DOI: 10.1145/2512469

Network coding is a well-known technique used to enhance network throughput and reliability by applying special coding to data packets. One critical problem in practice, when using the random linear network coding technique, is the high...

A constraint programming approach for integrated spatial and temporal scheduling for clustered architectures
Mirza Beg, Peter van Beek
Article No.: 14
DOI: 10.1145/2512470

Many embedded processors use clustering to scale up instruction-level parallelism in a cost-effective manner. In a clustered architecture, the registers and functional units are partitioned into smaller units and clusters communicate through...