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Hybrid systems combine discrete controllers with adjoining physical processes. While many approaches exist for simulating hybrid systems, there are few approaches for their emulation, especially when the actual physical plant is not available....
Complete and Practical Universal Instruction Selection
Gabriel Hjort Blindell, Mats Carlsson, Roberto Castañeda Lozano, Christian Schulte
Article No.: 119
In code generation, instruction selection chooses processor instructions to implement a program under compilation where code quality crucially depends on the choice of instructions. Using methods from combinatorial optimization, this paper...
An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors
Xuesong Su, Hui Wu, Jingling Xue
Article No.: 120
In real-time embedded system design, one major goal is to construct a feasible schedule. Whether a feasible schedule exists depends on the Worst-Case Execution Time (WCET) of each task. Consequently, it is important to minimize the WCET of each...
A Study of Dynamic Phase Adaptation Using a Dynamic Multicore Processor
Paul-Jules Micolet, Aaron Smith, Christophe Dubach
Article No.: 121
Heterogeneous processors such as ARM’s big.LITTLE have become popular for embedded systems. They offer a choice between running workloads on a high performance core or a low-energy core leading to increased energy efficiency. However, the...
Implementation of Partitioned Mixed-Criticality Scheduling on a Multi-Core Platform
Roman Trüb, Georgia Giannopoulou, Andreas Tretter, Lothar Thiele
Article No.: 122
Recent industrial trends favor the adoption of multi-core architectures for mixed-criticality applications. Although several mixed-criticality multi-core scheduling approaches have been proposed, currently there are few implementations on hardware...
Modern multiprocessor systems-on-chip (MpSoCs) offer tremendous power and performance optimization opportunities by tuning thousands of potential voltage, frequency and core configurations. As the workload phases change at runtime, different...
VLIW processors typically deliver high performance on limited budget making them ideal for a variety of communication and signal processing solutions. These processors typically need large multi-ported register files that can have side effects of...
An Out-of-Order Load-Store Queue for Spatial Computing
Lana Josipovic, Philip Brisk, Paolo Ienne
Article No.: 125
The efficiency of spatial computing depends on the ability to achieve maximal parallelism. This necessitates memory interfaces that can correctly handle memory accesses that arrive in arbitrary order while still respecting data dependencies and...
Diagonal Component Expansion for Flow-Layer Placement of Flow-Based Microfluidic Biochips
Brian Crites, Karen Kong, Philip Brisk
Article No.: 126
Continuous flow-based microfluidic devices have seen a huge increase in interest because of their ability to automate and miniaturize biochemistry and biological processes, as well as their promise of creating a programmable platform for chemical...
Synthesis of Error-Recovery Protocols for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Mahmoud Elfar, Zhanwei Zhong, Zipeng Li, Krishnendu Chakrabarty, Miroslav Pajic
Article No.: 127
A digital microfluidic biochip (DMFB) is an attractive technology platform for various biomedical applications. However, a conventional DMFB is limited by: (i) the number of electrical connections that can be practically realized, (ii) constraints...
IoT devices need reliable hardware at low cost. It is challenging to efficiently cope with both hard and soft faults in embedded scratchpad memories. To address this problem, we propose a two-step approach: FaultLink and Software-Defined...
The bottleneck between the processing elements and memory is the biggest issue contributing to the scalability problem in computing. In-memory computation is an alternative approach that combines memory and processor in the same location, and...
Arnab Raha, Vijay Raghunathan
Article No.: 130
Approximate computing has emerged as a popular design paradigm for optimizing the performance and energy consumption of error-resilient applications in domains such as machine learning, graphics, data analytics, etc. Numerous techniques for...
Frame rate has a direct impact on the energy consumption of smartphones: the higher the frame rate, the higher the power consumption. Hence, reducing display refreshes will reduce the power consumption. However, it is risky to manipulate frame...
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance
Hao Yan, Lei Jiang, Lide Duan, Wei-Ming Lin, Eugene John
Article No.: 132
Handheld devices, such as smartphones and tablets, currently dominate the semiconductor market. The memory access patterns of CPU and IP cores are dramatically different in a handheld device, making the main memory a critical bottleneck of the...
Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors
Siddharth Rai, Mainak Chaudhuri
Article No.: 133
Heterogeneous chip-multiprocessors with CPU and GPU integrated on the same die allow sharing of critical memory system resources among the CPU and GPU applications. Such architectures give rise to challenging resource scheduling problems. In this...
Reinforcement Learning-Assisted Garbage Collection to Mitigate Long-Tail Latency in SSD
Wonkyung Kang, Dongkun Shin, Sungjoo Yoo
Article No.: 134
NAND flash memory is widely used in various systems, ranging from real-time embedded systems to enterprise server systems. Because the flash memory has erase-before-write characteristics, we need flash-memory management methods, i.e., address...
Minimising Access Conflicts on Shared Multi-Bank Memory
Andreas Tretter, Georgia Giannopoulou, Matthias Baer, Lothar Thiele
Article No.: 135
A common multi-core pattern consists of processors communicating through shared, multi-banked on-chip memory. Two approaches exist: Interleaved address mapping, which spreads consecutive data over all banks, and contiguous address mapping, which...
CAMsure: Secure Content-Addressable Memory for Approximate Search
M. Sadegh Riazi, Mohammad Samragh, Farinaz Koushanfar
Article No.: 136
We introduce CAMsure, the first realization of secure Content Addressable Memory (CAM) in the context of approximate search using near-neighbor algorithms. CAMsure provides a lightweight solution for practical secure (approximate) search with a...
Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models
Luca Piccolboni, Alessandro Menon, Graziano Pravadelli
Article No.: 137
Only few solutions for Hardware Trojan (HT) detection work at Register-Transfer Level (RTL), thus delaying the identification of possible security issues at lower abstraction levels of the design process. In addition, the most of existing...
A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm
Vincent Migliore, Cédric Seguin, Maria Méndez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat, Russell Tessier
Article No.: 138
Somewhat Homomorphic Encryption (SHE) schemes can be used to carry out operations on ciphered data. In a cloud computing scenario, personal information can be processed secretly, inferring a high level of confidentiality. The principle limitation...
FlashKV: Accelerating KV Performance with Open-Channel SSDs
Jiacheng Zhang, Youyou Lu, Jiwu Shu, Xiongjun Qin
Article No.: 139
As the cost-per-bit of solid state disks is decreasing quickly, SSDs are supplanting HDDs in many cases, including the primary storage of key-value stores. However, simply deploying LSM-tree-based key-value stores on commercial SSDs is inefficient...
Flash memory is used as a main data storage medium in increasingly large areas of applications, rapidly replacing hard disk drives because of its low power consumption, fast random access, and high shock resistance. Such flash-based storage...
A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance
Fei Wu, Meng Zhang, Yajuan Du, Xubin He, Ping Huang, Changsheng Xie, Jiguang Wan
Article No.: 141
By scaling down to smaller cell size, NAND flash has significantly increased the storage capacity in order to lower the unit cost down. However, the reliability is sacrificed due to much higher raw bit error rates. As a result, conventional error...
P-Alloc: Process-Variation Tolerant Reliability Management for 3D Charge-Trapping Flash Memory
Yi Wang, Lisha Dong, Rui Mao
Article No.: 142
Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturbance, and lower access latency. In contrast to...
An Automated Security-Aware Approach for Design of Embedded Systems on MPSoC
Benjamin Tan, Morteza Biglari-Abhari, Zoran Salcic
Article No.: 143
MPSoC-based embedded systems design is becoming increasingly complex. Not only do we need to satisfy multiple design objectives, we increasingly need to address potential security risks. In this work, we propose a security-aware systematic design...
SoftRM: Self-Organized Fault-Tolerant Resource Management for Failure Detection and Recovery in NoC Based Many-Cores
Vasileios Tsoutsouras, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris
Article No.: 144
Many-core systems are envisioned to leverage the ever-increasing demand for more powerful computing systems. To provide the necessary computing power, the number of Processing Elements integrated on-chip increases and NoC based infrastructures are...
Power-Temperature Stability and Safety Analysis for Multiprocessor Systems
Ganapati Bhat, Suat Gumussoy, Umit Y. Ogras
Article No.: 145
Modern multiprocessor system-on-chips (SoCs) integrate multiple heterogeneous cores to achieve high energy efficiency. The power consumption of each core contributes to an increase in the temperature across the chip floorplan. In turn, higher...
CGPredict: Embedded GPU Performance Estimation from Single-Threaded Applications
Siqi Wang, Guanwen Zhong, Tulika Mitra
Article No.: 146
Heterogeneous multiprocessor system-on-chip architectures are endowed with accelerators such as embedded GPUs and FPGAs capable of general-purpose computation. The application developers for such platforms need to carefully choose the accelerator...
Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs
Amit Kumar Singh, Alok Prakash, Karunakar Reddy Basireddy, Geoff V. Merrett, Bashir M. Al-Hashimi
Article No.: 147
Heterogeneous Multi-Processor Systems-on-Chips (MPSoCs) containing CPU and GPU cores are typically required to execute applications concurrently. However, as will be shown in this paper, existing approaches are not well suited for concurrent...
This paper introduces a predictive modeling framework to estimate the performance of GPUs during pre-silicon design. Early-stage performance prediction is useful when simulation times impede development by rendering driver performance validation,...
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis
Pietro Fezzardi, Marco Lattuada, Fabrizio Ferrandi
Article No.: 149
High-Level Synthesis (HLS) for FPGAs is attracting popularity and is increasingly used to handle complex systems with multiple integrated components. To increase performance and efficiency, HLS flows now adopt several advanced optimization...
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators
Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
Article No.: 150
Hardware accelerators are key to the efficiency and performance of system-on-chip (SoC) architectures. With high-level synthesis (HLS), designers can easily obtain several performance-cost trade-off implementations for each component of a complex...
Machine Intelligence on Resource-Constrained IoT Devices: The Case of Thread Granularity Optimization for CNN Inference
Mohammad Motamedi, Daniel Fong, Soheil Ghiasi
Article No.: 151
Despite their remarkable performance in various machine intelligence tasks, the computational intensity of Convolutional Neural Networks (CNNs) has hindered their widespread utilization in resource-constrained embedded and IoT systems. To address...
Heterogeneous multi-processors are designed to bridge the gap between performance and energy efficiency in modern embedded systems. This is achieved by pairing Out-of-Order (OoO) cores, yielding performance through aggressive speculation...
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Article No.: 153
Scaling of semiconductor devices has enabled higher levels of integration and performance improvements at the price of making devices more susceptible to the effects of static and dynamic variability. Adding safety margins (guardbands) on the...
Efficient Virtual Memory Sharing via On-Accelerator Page Table Walking in Heterogeneous Embedded SoCs
Pirmin Vogel, Andreas Kurth, Johannes Weinbuch, Andrea Marongiu, Luca Benini
Article No.: 154
Shared virtual memory is key in heterogeneous systems on chip (SoCs) that combine a general-purpose host processor with a many-core accelerator, both for programmability and performance. In contrast to the full-blown, hardware-only solutions...
A DWM-Based Stack Architecture Implementation for Energy Harvesting Systems
Hoda Aghaei Khouzani, Chengmo Yang
Article No.: 155
Energy harvesting systems tend to use non-volatile processors to conduct computation under intermittent power supplies. While previous implementations of non-volatile processors are based on register architectures, stack architecture, known for...
Wearable devices with sensing, processing and communication capabilities have become feasible with the advances in internet-of-things (IoT) and low power design technologies. Energy harvesting is extremely important for wearable IoT devices due to...
Models of the cardiac conduction system are usually at two extremes: (1) high fidelity models with excellent precision but lacking a real-time response for emulation (hardware in the loop simulation); or (2) models amenable for emulation, but that...
RISE: An Automated Framework for Real-Time Intelligent Video Surveillance on FPGA
Bita Darvish Rouhani, Azalia Mirhoseini, Farinaz Koushanfar
Article No.: 158
This paper proposes RISE, an automated Reconfigurable framework for real-time background subtraction applied to Intelligent video SurveillancE. RISE is devised with a new streaming-based methodology that adaptively learns/updates a corresponding...
An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery
Soumya Basu, Loris Duch, RubÉn Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
Article No.: 159
The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible...
Online scheduling of operations is essential to optimize productivity of flexible manufacturing systems (FMSs) where manufacturing requests arrive on the fly. An FMS processes products according to a particular flow through processing stations....
Response Time Analysis for Sporadic Server Based Budget Scheduling in Real Time Virtualization Environments
Matthias Beckert, Rolf Ernst
Article No.: 161
Virtualization techniques for embedded real-time systems typically employ TDMA scheduling to achieve temporal isolation among different virtualized applications. Recent work already introduced sporadic server based solutions relying on budgets...
Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems
Xiaowen Chen, Zhonghai Lu, Sheng Liu, Shuming Chen
Article No.: 162
In 3D NoC-based many-core systems, DRAM accesses behave differently due to their different communication distances and the latency gap of different DRAM accesses becomes bigger as the network size increases, which leads to unfair DRAM access...
Recent embedded systems are becoming integrated systems with components of different criticality. To tackle this, mixed-criticality systems aim to provide different levels of timing assurance to components of different criticality levels while...
Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures
Benjamin Rouxel, Steven Derrien, Isabelle Puaut
Article No.: 164
Multi-core systems are increasingly interesting candidates for executing parallel real-time applications, in avionic, space or automotive industries, as they provide both computing capabilities and power efficiency. However, ensuring that timing...
On The Design and Application of Thermal Isolation Servers
Rehan Ahmed, Pengcheng Huang, Max Millen, Lothar Thiele
Article No.: 165
Recently, there has been an increasing trend towards executing real-time applications on multi-core platforms. However, this complicates the design problem, as applications running on different cores can interfere due to shared resources and...
We introduce a new method to compute non-convex invariants of numerical programs, which includes the class of switched affine systems with affine guards. We obtain disjunctive and non-convex invariants by associating different partial execution...
This paper proposes the use of static analysis to improve the generation of invariants from test data extracted from Simulink models. Previous work has shown the utility of such automatically generated invariants as a means for updating and...
Formal Verification of a Timing Enforcer Implementation
Sagar Chaki, Dionisio De Niz
Article No.: 168
A timing enforcer is a scheduler that not only allocates CPU cycles to threads, but also uses timers to enforce time budgets. An approach for verifying safety properties of timing enforcers at the source code level is presented. We assume that the...
Timestamp Temporal Logic (TTL) for Testing the Timing of Cyber-Physical Systems
Mohammadreza Mehrabian, Mohammad Khayatian, Aviral Shrivastava, John C. Eidson, Patricia Derler, Hugo A. Andrade, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss, Kevin Stanton
Article No.: 169
In order to test the performance and verify the correctness of Cyber-Physical Systems (CPS), the timing constraints on the system behavior must be met. Signal Temporal Logic (STL) can efficiently and succinctly capture the timing constraints of a...
Many problems in the design and analysis of cyber-physical systems (CPS) reduce to the following optimization problem: given a CPS which transforms continuous-time input traces in Rm to continuous-time output traces in...
Weakly Hard Schedulability Analysis for Fixed Priority Scheduling of Periodic Real-Time Tasks
Youcheng Sun, Marco Di Natale
Article No.: 171
The hard deadline model is very popular in real-time research, but is representative or applicable to a small number of systems. Many applications, including control systems, are capable of tolerating occasional deadline misses, but are seriously...
Response-Time Analysis for Task Chains with Complex Precedence and Blocking Relations
Johannes Schlatow, Rolf Ernst
Article No.: 172
For the development of complex software systems, we often resort to component-based approaches that separate the different concerns, enhance verifiability and reusability, and for which microkernel-based implementations are a good fit to enforce...
An Abstraction-Refinement Theory for the Analysis and Design of Real-Time Systems
Philip S. Kurtin, Marco J. G. Bekooij
Article No.: 173
Component-based and model-based reasonings are key concepts to address the increasing complexity of real-time systems. Bounding abstraction theories allow to create efficiently analyzable models that can be used to give temporal or functional...
HiCH: Hierarchical Fog-Assisted Computing Architecture for Healthcare IoT
Iman Azimi, Arman Anzanpour, Amir M. Rahmani, Tapio Pahikkala, Marco Levorato, Pasi Liljeberg, Nikil Dutt
Article No.: 174
The Internet of Things (IoT) paradigm holds significant promises for remote health monitoring systems. Due to their life- or mission-critical nature, these systems need to provide a high level of availability and accuracy. On the one hand,...
Optimization of Real-Time Software Implementing Multi-Rate Synchronous Finite State Machines
Yecheng Zhao, Chao Peng, Haibo Zeng, Zonghua Gu
Article No.: 175
Model-based design using Synchronous Reactive (SR) models is becoming widespread for control software development in industry. However, software synthesis is challenging for multi-rate SR models consisting of blocks modeled with finite state...
Hybrid systems modelers like Simulink come with a rich collection of discrete-time and continuous-time blocks. Most blocks are not defined in terms of more elementary ones—and some cannot be—but are instead written in imperative...
Timing Analysis of Synchronous Programs using WCRT Algebra: Scalability through Abstraction
Jiajie Wang, Michael Mendler, Partha Roop, Bruno Bodin
Article No.: 177
Synchronous languages are ideal for designing safety-critical systems. Static Worst-Case Reaction Time (WCRT) analysis is an essential component in the design flow that ensures the real-time requirements are met. There are a few approaches for...
Many implantable medical devices, such as pacemakers, have been recalled due to failure of their embedded software. This motivates rethinking their design and certification processes. We propose, for the first time, an additional layer of safety...
This paper presents BenchPrime, an automated benchmark analysis toolset that is systematic and extensible to analyze the similarity and diversity of benchmark suites. BenchPrime takes multiple benchmark suites and their evaluation metrics as...
Demystifying Soft-Error Mitigation by Control-Flow Checking -- A New Perspective on its Effectiveness
Simon Schuster, Peter Ulbrich, Isabella Stilkerich, Christian Dietrich, Wolfgang SchröDer-Preikschat
Article No.: 180
Soft errors are a challenging and urging problem in the domain of safety-critical embedded systems. For decades, checking schemes have been investigated and improved to mitigate soft-error effects for the class of control-flow faults, with current...
Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning
Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
Article No.: 181
In this paper, we present an adaptive power manager for solar energy harvesting sensor nodes. We use a simplified model consisting of a solar panel, an ideal battery and a general sensor node with variable duty cycle. Our power manager uses...
There has been a constant demand for memory in modern mobile systems to provide users with better experience. Swapping is one of the cost-effective software solutions to provide extra usable memory by reclaiming inactive pages and improving memory...
Data compression is beneficial to flash storage lifespan. However, because the design of mobile flash storage is highly cost-sensitive, hardware compression becomes a less attractive option. This study investigates the feasibility of data...
Managing the Performance/Error Tradeoff of Floating-point Intensive Applications
Ramy Medhat, Michael O. Lam, Barry L. Rountree, Borzoo Bonakdarpour, Sebastian Fischmeister
Article No.: 184
Modern embedded systems are becoming more reliant on real-valued arithmetic as they employ mathematically complex vision algorithms and sensor signal processing. Double-precision floating point is the most commonly used precision in computer...
In this article we study ways of constructing meaningful operational models of piecewise-smooth systems (PWS). The systems we consider are described by polynomial vector fields defined on non-overlapping semi-algebraic sets, which form a partition...
The problem of probabilistic safety verification of stochastic hybrid systems is to check whether the probability that a given system will reach an unsafe region from certain initial states can be bounded by some given probability threshold. The...
Compositional Relational Abstraction for Nonlinear Hybrid Systems
Xin Chen, Sergio Mover, Sriram Sankaranarayanan
Article No.: 187
We propose techniques to construct abstractions for nonlinear dynamics in terms of relations expressed in linear arithmetic. Such relations are useful for translating the closed loop verification problem of control software with continuous-time,...
Security-Aware Scheduling of Embedded Control Tasks
Vuk Lesi, Ilija Jovanov, Miroslav Pajic
Article No.: 188
In this work, we focus on securing cyber-physical systems (CPS) in the presence of network-based attacks, such as Man-in-the-Middle (MitM) attacks, where a stealthy attacker is able to compromise communication between system sensors and...
A Structured Methodology for Pattern based Adaptive Scheduling in Embedded Control
Sumana Ghosh, Souradeep Dutta, Soumyajit Dey, Pallab Dasgupta
Article No.: 189
Software implementation of multiple embedded control loops often share compute resources. The control performance of such implementations have been shown to improve if the sharing of bandwidth between control loops can be dynamically regulated in...
We present Antlab, an end-to-end system that takes streams of user task requests and executes them using collections of robots. In Antlab, each request is specified declaratively in linear temporal logic extended with quantifiers over robots. The...