Worst-case-based timing verification for the controller area network (CAN) has been bottleneck in efficient use of its bandwidth. Especially, this inefficiency comes from the worst-case transmission error rate (WCTER) when accounting transmission errors. To alleviate this inefficiency, we propose a runtime adaptation scheme, error-adaptive CAN (EACAN). EACAN observes the behavior of transmission errors at runtime, and reconfigures the periods of messages based on the observation to satisfy of the requirement of timing failure. We experimentally evaluated the bandwidth utilization with usage of EACAN and WCTER-based verification. The results show that EACAN improves the bandwidth utilization by 15% over WCTER-based verification.
Editorial: Human Factors in Embedded Computing
Contemporary many-core architectures such as Adapteva Epiphany and Sunway TaihuLight, employ per-core Scratchpad Memory (SPM) for better performance-per-watt. A core is allowed to access its local and remote SPMs through the Network-On-Chip. However, the compiler/programmer is required to explicitly manage data movement. Utilizing SPMs for multi-threaded applications is more challenging, as the shared variables need to be placed appropriately. We present a compile-time framework that automatically identifies shared/private variables and places them to suitable memory. Experimental evaluation on the Parallella platform confirms that our strategy reduces the execution time and energy consumption by 1.84x/1.83x when compared to the existing approaches.
The Internet of Things (IoT) is expanding at a large rate, with devices found in commercial and domestic settings from industrial sensors to home appliances. However, as the IoT market grows, so does the number of attacks made against it with some reports claiming an increase of 600\% in 2017. This work seeks to prevent code replacement, injection and exploitation attacks by ensuring correct and platform specific application execution. This combines two previously studied problems: secure application execution and binding hardware and software. We present descriptions of both problems and requirements for ensuring both simultaneously. We then propose a scheme extending previous work that meets these requirements, and describe our implementation of the soft-core Secure Execution Processor developed and tested on Xilinx Spartan-6 FPGA. Finally, we analyse the scheme and our implementation according to performance and the requirements listed.
We present a technique for implementing dataflow networks as compositional hardware circuits. We first define an abstract dataflow model with unbounded buffers that supports data-dependent blocks (mux, demux, and nondeterministic merge); we then show how to faithfully implement such networks with bounded buffers and handshaking. Handshaking admits compositionality: our circuits can be connected with or without buffers and still compute the same function without introducing spurious combinational cycles. As such, inserting or removing buffers affects the performance but not the functionality of our networks; which we demonstrate through experiments that show how design space can be explored.
Present semiconductor design industry has embraced the globalization strategy for System on Chip(SoC) design.However, attacks due to vulnerability of hardware like Hardware Trojans and counterfeiting has raised significant concerns.Both root of untrust may be undetectable during testing but may get exhibited via sudden performance degradation at runtime.Threat analysis is performed for real time SoC operations due to sudden performance degradation of any of the SoC components, procured from untrusted third party vendors.Refuge is sought to stigmergic behavior exhibited in insect colonies to propose a decentralized self aware security mechanism.Experimental validation and low overhead depicts prospect of our proposed approach.
With the popularity of modern FPGAs, the business of FPGA specific intellectual properties (IP) is expanding rapidly. This also brings in the concern of IP protection. FPGA vendors are making serious efforts for IP protection leading to standardization schemes like IEEE P1735. However, efficient techniques to prevent unauthorized overuse of IP still remain an open question. In this paper, we propose a two-party IP protection scheme combining the re-configurable LUT (RLUT) primitive of modern FPGAs with physically unclonable functions (PUF). The proposed scheme is considerably lightweight compared to existing schemes, prevents overuse and does not involve FPGA vendors or trusted third parties for IP licensing. The validation of the proposed scheme is done on MCNC'91 benchmark and third party IPs like AES and lightweight MIPS processor.
Implantable closed-loop neuromodulation devices for use in long-term chronic studies in a lab or clinical trial are expensive to acquire and difficult to modify for specific use cases. This work documents the design and fabrication of a wireless implantable device using only commercially available off-the-shelf (COTS) components. This device, called the Bionode, can record and transmit up to four channels of biopotential data while simultaneously providing biphasic constant-current stimulation. The Bionode is a viable, low-cost, recyclable, and easily modifiable research tool with clinical implications that has gained widespread use in various research projects at Purdue University.
This work introduces a heuristic-guided branching search algorithm for model-based, mutation-driven test case generation. The algorithm is designed towards the efficient and computationally tractable exploration of discrete, non-deterministic models with huge state spaces. Asynchronous parallel processing is a key feature of the algorithm. The algorithm is inspired by the successful path planning algorithm Rapidly exploring Random Trees (RRT). We adapt RRT in several aspects towards test case generation. Most notably, we introduce parametrized heuristics for start and successor state selection, as well as a mechanism to construct test cases from the data produced during search.
Huge leaps in performance and power improvements of computing systems are driven by rapid technology scaling, but technology scaling has also rendered computing systems susceptible to soft errors. Among the soft error protection techniques, Control Flow Checking (CFC) based techniques have gained a reputation of being lightweight yet effective. The main idea behind CFCs is to check if the program is executing the instructions in the right order. In order to validate the protection claims of existing CFCs, we develop a systematic and quantitative method to evaluate the protection achieved by CFCs using the metric of vulnerability. Our quantitative analysis indicates that existing CFC techniques are not only ineffective in providing protection from soft faults, but incur additional performance and power overheads. Our results show that software-only CFC protection schemes increase system vulnerability by 18% to 21% with 17% to 38% performance overhead and hybrid CFC protection increases vulnerability by 5%. Although the vulnerability remains almost the same for hardware only CFC protection, they incur overheads of design cost, area, and power due to the hardware modifications required for their implementations.
With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for Internet based on classical cryptography cannot be applied to IoT nodes due to the resource-constrained platform. A physical unclonable function (PUF) can be used to generate a key online or uniquely identify an integrated circuits (ICs) by extracting its internal random differences using the so-called challenge-response pairs (CRPs). The PUF is a new type of hardware-based security primitive; it is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This paper first presents a new classification of RPUFs into circuit based RPUF (C-RPUF) and algorithm based RPUF (A-RPUF); two XOR-based RPUF circuits (namely the XOR-based reconfigurable bistable ring PUF (XRBR PUF) and the XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented using Xilinx Spartan-6 FPGAs. The implementation results are compared with previous PUF designs showing a good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response; this confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability.
We develop an assume-guarantee contract framework for cyber-physical system design under probabilistic requirements. Given a stochastic linear system and a set of requirements captured by bounded Stochastic Signal Temporal Logic (StSTL) contracts, we propose algorithms to check contract compatibility, consistency, and refinement, and generate a control trajectory that satisfies a contract. We leverage encodings of the verification and control synthesis tasks into mixed integer optimization problems, and conservative approximations of probabilistic constraints that produce sound and tractable problem formulations. We illustrate the effectiveness of our approach on a few examples, including the design of controllers for aircraft power distribution networks.
Recently, the popularity of smart-devices (e.g., IoT devices or smartphones) has led to a rapid development and significant advancement of ubiquitous applications for mobile commerce around the world. Novel transaction schemes, such as Apple Pay, Android Pay and Samsung Pay, are becoming a more popular way for new types of payments no matter what type of smart IoT-devices are used. Due to the promptly growing importance of security, a great deal of attention has come to the topic of how to construct a robust transaction protocol during online payments. In this study, we demonstrate a lightweight cryptographic protocol based on a sturdy certificateless signature scheme with robust bilinear pairing crypto-primitives. We elegantly refine the proposed cryptographic protocol to account for computation-limited smart-devices during transaction. The practicability of the proposed protocol is then guaranteed via a rigorous security analysis and a thorough performance evaluation conducted by us, where an IoT-based test-bed, i.e. the Raspberry PI platform, is acted as a underlying architecture of the implementation of our proposed cryptographic protocol.
During the formal functional verification of RTL designs, a false failure is often observed. Most of the time, this failure is caused by an under-constrained model. The analysis of the root cause for the verification error and the creation of missing assumptions are a significant time burden. In this paper, we present a methodology to automatically mine these missing assumptions from counter-examples. First, multiple counter-examples are generated for the same property. Then, relevant behaviors are mined from the counter-examples. Finally, corresponding assumptions are filtered, and a small number of them is returned to the user for review.
Convolutional Neural Networks (CNN) have been widely deployed in diverse application domains. There has been significant progress in accelerating both their training and inference using high-performance GPUs, FPGAs, and custom ASICs for datacenter-scale environments. The recent proliferation of mobile and IoT devices have necessitated real-time, energy-efficient deep neural network inference on embedded-class, resource-constrained platforms. In this context, we present Synergy, an automated, hardware-software co-designed, pipelined, high-throughput CNN inference framework on embedded heterogeneous system-on-chip (SoC) architectures (Xilinx Zynq). Synergy leverages, through multi-threading, all the available on-chip resources, which includes the dual-core ARM processor along with the FPGA and the NEON SIMD engines as accelerators. Moreover, Synergy provides a unified abstraction of the heterogeneous accelerators (FPGA and NEON) and can adapt to different network configurations at runtime without changing the underlying hardware accelerator architecture by balancing workload across accelerators through work-stealing. Synergy achieves 7.3x speedup, averaged across seven CNN models, over a well-optimized software-only solution. Synergy demonstrates substantially better throughput and energy-efficiency compared to the contemporary CNN implementations on the same SoC architecture.
In the growing Internet of Things context, thousands of computing devices with various functionalities are producing data (from environmental sensors or other sources). However, they are also collecting, storing, processing and transmitting data to eventually communicate them securely to third parties (e.g. owners of devices or cloud data storage). The deployed devices are often battery-powered mobile or static nodes equipped with sensors and/or actuators and they communicate using wireless technologies. Examples include unmanned aerial vehicles, wireless sensor nodes, smart beacons, and wearable health objects. Such resource-constrained devices include Active RFID (Radio Frequency IDentification) nodes and these are used to illustrate our proposal. In most scenarios, these nodes are unattended in an adverse environment, so data confidentiality must be ensured from the sensing phase through to delivery to authorized entities: in other words, data must be securely stored and transmitted to prevent attack by active adversaries even if the nodes are captured. However, due to the scarce resources available to nodes in terms of energy, storage and/or computation, the proposed security solution has to be lightweight. In this paper, we propose a serverless protocol to enable MDCs (Mobile Data Collectors), such as drones, to securely collect data from mobile and static Active RFID nodes and then deliver them later to an authorized third party. The whole solution ensures data confidentiality at each step (from the sensing phase, before data collection by the MDC, once data have been collected by MDC, and during final delivery) while fulfilling the lightweight requirements for the resource-limited entities involved. To assess the suitability of the protocol against the performance requirements, it was implemented on the most resource-constrained devices to get the worst possible results. In addition, to prove the protocol fulfills the security requirements, it was analyzed with regard to security games and also formally verified using the AVISPA tool.